PIC24 Support Libraries
pic24_configbits.c
Go to the documentation of this file.
1 /*
2  * "Copyright (c) 2008 Robert B. Reese, Bryan A. Jones, J. W. Bruce ("AUTHORS")"
3  * All rights reserved.
4  * (R. Reese, reese_AT_ece.msstate.edu, Mississippi State University)
5  * (B. A. Jones, bjones_AT_ece.msstate.edu, Mississippi State University)
6  * (J. W. Bruce, jwbruce_AT_ece.msstate.edu, Mississippi State University)
7  *
8  * Permission to use, copy, modify, and distribute this software and its
9  * documentation for any purpose, without fee, and without written agreement is
10  * hereby granted, provided that the above copyright notice, the following
11  * two paragraphs and the authors appear in all copies of this software.
12  *
13  * IN NO EVENT SHALL THE "AUTHORS" BE LIABLE TO ANY PARTY FOR
14  * DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT
15  * OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE "AUTHORS"
16  * HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
17  *
18  * THE "AUTHORS" SPECIFICALLY DISCLAIMS ANY WARRANTIES,
19  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
20  * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS
21  * ON AN "AS IS" BASIS, AND THE "AUTHORS" HAS NO OBLIGATION TO
22  * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
23  *
24  * Please maintain this header in its entirety when copying/modifying
25  * these files.
26  *
27  *
28  */
29 
30 
31 // Documentation for this file. If the \file tag isn't present,
32 // this file won't be documented.
33 /** \file
34  * This file contains configuration bit settings. To add more chips:
35  *
36  * 1. Add the appropriate \#if __chip_name__ / \#endif pair (copy the format of
37  * other chips below.)
38  * 2. Open the configuration bits editor in the MPLAB X IDE and select the
39  * appropriate bits for your chip.
40  * 3. Click "Generate Source Code To Output", then copy and paste the output
41  * inside the \#if / \#endif pair you added.
42  * 4. Delete the settings for FNOSC, POSCMD / POSCMOD, and OSCIOFNC; these
43  * will be set based on the clock configuration.
44  *
45  */
46 #include "pic24_clockfreq.h"
47 
48 // *****************************************
49 // Settings based on clock choice begin here
50 // *****************************************
51 // These should not typically be edited.
52 
53 #ifdef BOOTLOADER
54 // POSCMD_XT: Select bootloader config bits which allow user code to optionally
55 // use an XT oscillator. Change this for an HS crystal or an external clock (EC).
56 # undef POSCMD_SEL
57 # define POSCMD_SEL POSCMD_XT
58 
59 // OSCIOFNC_OFF: Reserve OSC2 as a potential crystal pin, instead of making it
60 // a digital I/O pin.
61 # define OSCIOFNC_SEL OSCIOFNC_OFF
62 #else
63 // Enable/disable OSC IO pins based on oscillator selection.
64 # if POSCMD_SEL == POSCMD_NONE
65 // Make the OSC2 pin a digital I/O.
66 # define OSCIOFNC_SEL OSCIOFNC_ON
67 # else
68 // Reserve the OSC pins for use with an oscillator (HS and XT modes) or
69 // have it output the clock (EC mode).
70 # define OSCIOFNC_SEL OSCIOFNC_OFF
71 # endif
72 #endif
73 
74 /* Note on clock choice: The processor is configured to always
75  * start up with the FRC, rather than what it will use after
76  * clock configuration. This guarantees a working clock at
77  * power-up, which can then be changed by the bootloader / user
78  * code / etc.
79  */
80 // FOSCSEL
81 # pragma config FNOSC = FRC // Oscillator Source Selection (Internal Fast RC (FRC))
82 
83 // Translate the selected primary oscillator source to # pragma-style configs for the FOSC register.
84 #if defined(__PIC24F__) || defined(__PIC24FK__)
85 // The PIC24F/FK calls this config bit POSCMOD.
86 # if POSCMD_SEL == POSCMD_EC
87 # pragma config POSCMOD = EC // Primary Oscillator Mode Select bits (EC Crystal Oscillator Mode)
88 # elif POSCMD_SEL == POSCMD_XT
89 # pragma config POSCMOD = XT // Primary Oscillator Mode Select bits (XT Crystal Oscillator Mode)
90 # elif POSCMD_SEL == POSCMD_HS
91 # pragma config POSCMOD = HS // Primary Oscillator Mode Select bits (HS Crystal Oscillator Mode)
92 # elif POSCMD_SEL == POSCMD_NONE
93 # pragma config POSCMOD = NONE // Primary Oscillator Mode Select bits (Primary Oscillator disabled)
94 # else
95 # error "Unknown primary oscillator selection."
96 # endif
97 #else
98 // All other processors call it POSCMD.
99 # if POSCMD_SEL == POSCMD_EC
100 # pragma config POSCMD = EC // Primary Oscillator Mode Select bits (EC Crystal Oscillator Mode)
101 # elif POSCMD_SEL == POSCMD_XT
102 # pragma config POSCMD = XT // Primary Oscillator Mode Select bits (XT Crystal Oscillator Mode)
103 # elif POSCMD_SEL == POSCMD_HS
104 # pragma config POSCMD = HS // Primary Oscillator Mode Select bits (HS Crystal Oscillator Mode)
105 # elif POSCMD_SEL == POSCMD_NONE
106 # pragma config POSCMD = NONE // Primary Oscillator Mode Select bits (Primary Oscillator disabled)
107 # else
108 # error "Unknown primary oscillator selection."
109 # endif
110 #endif
111 
112 // Translate the OSCIOFNC_SEL to # pragma-style configs for the FOSC register.
113 #if OSCIOFNC_SEL == OSCIOFNC_OFF
114 # pragma config OSCIOFNC = OFF // OSC2 Pin Function bit (OSC2 is clock output)
115 #elif OSCIOFNC_SEL == OSCIOFNC_ON
116 # pragma config OSCIOFNC = ON // OSC2 Pin Function bit (OSC2 is general purpose digital I/O pin)
117 #else
118 # error "Unknown OSCIOFNC selection."
119 #endif
120 
121 
122 // **************************************
123 // Settings for specific chips begin here
124 // **************************************
125 // Add new chips to the end of this file.
126 #if defined(__PIC24HJ12GP202__) || \
127  defined(__PIC24HJ12GP201__) || \
128  defined(__PIC24HJ32GP202__) || \
129  defined(__PIC24HJ16GP304__)
130 
131 
132 // FBS
133 # pragma config BWRP = WRPROTECT_OFF // Boot Segment Write Protect (Boot Segment may be written)
134 # pragma config BSS = NO_FLASH // Boot Segment Program Flash Code Protection (No Boot program Flash segment)
135 
136 // FGS
137 # pragma config GWRP = OFF // General Code Segment Write Protect (User program memory is not write-protected)
138 # pragma config GSS = OFF // General Segment Code Protection (User program memory is not code-protected)
139 
140 // FOSCSEL
141 # pragma config IESO = OFF // Internal External Switch Over Mode (Start-up device with user-selected oscillator source)
142 
143 // FOSC
144 # pragma config IOL1WAY = OFF // Peripheral Pin Select Configuration (Allow Multiple Re-configurations)
145 # pragma config FCKSM = CSECMD // Clock Switching and Monitor (Clock switching is enabled, Fail-Safe Clock Monitor is disabled)
146 
147 // FWDT
148 # pragma config WDTPOST = PS512 // Watchdog Timer Postscaler (1:512)
149 # pragma config WDTPRE = PR128 // WDT Prescaler (1:128)
150 # pragma config WINDIS = OFF // Watchdog Timer Window (Watchdog Timer in Non-Window mode)
151 # pragma config FWDTEN = OFF // Watchdog Timer Enable (Watchdog timer enabled/disabled by user software)
152 
153 // FPOR
154 # pragma config FPWRT = PWR16 // POR Timer Value (16ms)
155 # pragma config ALTI2C = OFF // Alternate I2C pins (I2C mapped to SDA1/SCL1 pins)
156 
157 // FICD
158 # pragma config ICS = PGD1 // Comm Channel Select (Communicate on PGC1/EMUC1 and PGD1/EMUD1)
159 # pragma config JTAGEN = OFF // JTAG Port Enable (JTAG is Disabled)
160 
161 ///\cond doxygen_ignore
162 # define CONFIG_BITS_DEFINED
163 ///\endcond
164 #endif // #ifdef (lots of PIC24H devices)
165 
166 
167 #if HARDWARE_PLATFORM == EXPLORER16_100P && defined(__PIC24HJ256GP610__)
168 
169 // FBS
170 # pragma config BWRP = WRPROTECT_OFF // Boot Segment Write Protect (Boot Segment may be written)
171 # pragma config BSS = NO_FLASH // Boot Segment Program Flash Code Protection (No Boot program Flash segment)
172 # pragma config RBS = NO_RAM // Boot Segment RAM Protection (No Boot RAM)
173 
174 // FSS
175 # pragma config SWRP = WRPROTECT_OFF // Secure Segment Program Write Protect (Secure segment may be written)
176 # pragma config SSS = NO_FLASH // Secure Segment Program Flash Code Protection (No Secure Segment)
177 # pragma config RSS = NO_RAM // Secure Segment Data RAM Protection (No Secure RAM)
178 
179 // FGS
180 # pragma config GWRP = OFF // General Code Segment Write Protect (User program memory is not write-protected)
181 # pragma config GSS = OFF // General Segment Code Protection (User program memory is not code-protected)
182 
183 // FOSCSEL
184 # pragma config IESO = OFF // Two-speed Oscillator Start-Up Enable (Start up with user-selected oscillator)
185 
186 // FOSC
187 # pragma config FCKSM = CSECMD // Clock Switching and Monitor (Clock switching is enabled, Fail-Safe Clock Monitor is disabled)
188 
189 // FWDT
190 # pragma config WDTPOST = PS512 // Watchdog Timer Postscaler (1:512)
191 # pragma config WDTPRE = PR128 // WDT Prescaler (1:128)
192 # pragma config WINDIS = OFF // Watchdog Timer Window (Watchdog Timer in Non-Window mode)
193 # pragma config FWDTEN = OFF // Watchdog Timer Enable (Watchdog timer enabled/disabled by user software)
194 
195 // FPOR
196 # pragma config FPWRT = PWR16 // POR Timer Value (16ms)
197 
198 // FICD
199 # pragma config ICS = PGD1 // Comm Channel Select (Communicate on PGC1/EMUC1 and PGD1/EMUD1)
200 # pragma config JTAGEN = OFF // JTAG Port Enable (JTAG is Disabled)
201 
202 ///\cond doxygen_ignore
203 # define CONFIG_BITS_DEFINED
204 ///\endcond
205 #endif
206 
207 
208 #if defined(__PIC24FJ64GA002__)
209 
210 // CONFIG2
211 # pragma config I2C1SEL = PRI // I2C1 Pin Location Select (Use default SCL1/SDA1 pins)
212 # pragma config IOL1WAY = OFF // IOLOCK Protection (IOLOCK may be changed via unlocking seq)
213 # pragma config FCKSM = CSECMD // Clock Switching and Monitor (Clock switching is enabled, Fail-Safe Clock Monitor is disabled)
214 # pragma config SOSCSEL = SOSC // Sec Oscillator Select (Default Secondary Oscillator (SOSC))
215 # pragma config WUTSEL = LEG // Wake-up timer Select (Legacy Wake-up Timer)
216 # pragma config IESO = OFF // Internal External Switch Over Mode (IESO mode (Two-Speed Start-up) disabled)
217 
218 // CONFIG1
219 # pragma config WDTPS = PS512 // Watchdog Timer Postscaler (1:512)
220 # pragma config FWPSA = PR128 // WDT Prescaler (Prescaler ratio of 1:128)
221 # pragma config WINDIS = OFF // Watchdog Timer Window (Windowed Watchdog Timer enabled; FWDTEN must be 1)
222 # pragma config FWDTEN = OFF // Watchdog Timer Enable (Watchdog Timer is disabled)
223 # pragma config ICS = PGx1 // Comm Channel Select (Emulator EMUC1/EMUD1 pins are shared with PGC1/PGD1)
224 # pragma config GWRP = OFF // General Code Segment Write Protect (Writes to program memory are allowed)
225 # pragma config GCP = OFF // General Code Segment Code Protect (Code protection is disabled)
226 # pragma config JTAGEN = OFF // JTAG Port Enable (JTAG port is disabled)
227 
228 ///\cond doxygen_ignore
229 # define CONFIG_BITS_DEFINED
230 ///\endcond
231 #endif // #ifdef PIC24F processors
232 
233 #if HARDWARE_PLATFORM == EXPLORER16_100P && defined(__PIC24FJ128GA010__)
234 
235 // CONFIG2
236 # pragma config FCKSM = CSECMD // Clock Switching and Monitor (Clock switching is enabled, Fail-Safe Clock Monitor is disabled)
237 # pragma config IESO = OFF // Internal External Switch Over Mode (IESO mode (Two-Speed Start-up) disabled)
238 
239 // CONFIG1
240 # pragma config WDTPS = PS512 // Watchdog Timer Postscaler (1:512)
241 # pragma config FWPSA = PR128 // WDT Prescaler (Prescaler ratio of 1:128)
242 # pragma config WINDIS = OFF // Watchdog Timer Window (Windowed Watchdog Timer enabled; FWDTEN must be 1)
243 # pragma config FWDTEN = OFF // Watchdog Timer Enable (Watchdog Timer is disabled)
244 # pragma config ICS = PGx1 // Comm Channel Select (Emulator/debugger uses EMUC1/EMUD1)
245 # pragma config GWRP = OFF // General Code Segment Write Protect (Writes to program memory are allowed)
246 # pragma config GCP = OFF // General Code Segment Code Protect (Code protection is disabled)
247 # pragma config JTAGEN = OFF // JTAG Port Enable (JTAG port is disabled)
248 
249 ///\cond doxygen_ignore
250 #define CONFIG_BITS_DEFINED
251 ///\endcond
252 #endif
253 
254 #if defined(__PIC24FJ64GB002__) || (__PIC24FJ64GB004__)
255 
256 // CONFIG4
257 # pragma config DSWDTPS = DSWDTPSF // DSWDT Postscale Select (1:2,147,483,648 (25.7 days))
258 # pragma config DSWDTOSC = LPRC // Deep Sleep Watchdog Timer Oscillator Select (DSWDT uses Low Power RC Oscillator (LPRC))
259 # pragma config RTCOSC = SOSC // RTCC Reference Oscillator Select (RTCC uses Secondary Oscillator (SOSC))
260 # pragma config DSBOREN = OFF // Deep Sleep BOR Enable bit (BOR disabled in Deep Sleep)
261 # pragma config DSWDTEN = OFF // Deep Sleep Watchdog Timer (DSWDT disabled)
262 
263 // CONFIG3
264 # pragma config WPFP = WPFP63 // Write Protection Flash Page Segment Boundary (Highest Page (same as page 42))
265 # pragma config SOSCSEL = SOSC // Secondary Oscillator Pin Mode Select (SOSC pins in Default (high drive-strength) Oscillator Mode)
266 # pragma config WUTSEL = LEG // Voltage Regulator Wake-up Time Select (Default regulator start-up time used)
267 # pragma config WPDIS = WPDIS // Segment Write Protection Disable (Segmented code protection disabled)
268 # pragma config WPCFG = WPCFGDIS // Write Protect Configuration Page Select (Last page and Flash Configuration words are unprotected)
269 # pragma config WPEND = WPENDMEM // Segment Write Protection End Page Select (Write Protect from WPFP to the last page of memory)
270 
271 // CONFIG2
272 # pragma config I2C1SEL = PRI // I2C1 Pin Select bit (Use default SCL1/SDA1 pins for I2C1 )
273 # pragma config IOL1WAY = OFF // IOLOCK One-Way Set Enable (The IOLOCK bit can be set and cleared using the unlock sequence)
274 # pragma config FCKSM = CSECMD // Clock Switching and Fail-Safe Clock Monitor (Sw Enabled, Mon Disabled)
275 # pragma config PLL96MHZ = OFF // 96MHz PLL Startup Select (96 MHz PLL Startup is enabled by user in software( controlled with the PLLEN bit))
276 # pragma config PLLDIV = DIV2 // USB 96 MHz PLL Prescaler Select (Oscillator input divided by 2 (8 MHz input))
277 # pragma config IESO = OFF // Internal External Switchover (IESO mode (Two-Speed Start-up) disabled)
278 
279 // CONFIG1
280 # pragma config WDTPS = PS512 // Watchdog Timer Postscaler (1:512)
281 # pragma config FWPSA = PR128 // WDT Prescaler (Prescaler ratio of 1:128)
282 # pragma config WINDIS = OFF // Windowed WDT (Standard Watchdog Timer enabled,(Windowed-mode is disabled))
283 # pragma config FWDTEN = OFF // Watchdog Timer (Watchdog Timer is disabled)
284 # pragma config ICS = PGx1 // Emulator Pin Placement Select bits (Emulator functions are shared with PGEC1/PGED1)
285 # pragma config GWRP = OFF // General Segment Write Protect (Writes to program memory are allowed)
286 # pragma config GCP = OFF // General Segment Code Protect (Code protection is disabled)
287 # pragma config JTAGEN = OFF // JTAG Port Enable (JTAG port is disabled)
288 
289 ///\cond doxygen_ignore
290 # define CONFIG_BITS_DEFINED
291 ///\endcond
292 #endif
293 
294 /***********************************************************************************
295 *** The dsPIC33ExxGP5xx and dsPIC33ExxGP8xx devices we use have slightly different
296 *** config bits defined. So we will look for our device and setup config bits
297 *** accordingly. As other devices are added, hopefully they won't differ from these
298 *** two cases....
299 *** .. until Microchip makes another small, subtle change in the datasheets (UGH!)
300 ***********************************************************************************/
301 #if defined(__dsPIC33EP128GP502__) || (__dsPIC33EP128GP504__)
302 
303 // FICD
304 # pragma config ICS = PGD1 // ICD Communication Channel Select bits (Communicate on PGEC1 and PGED1)
305 # pragma config JTAGEN = OFF // JTAG Enable bit (JTAG is disabled)
306 
307 // FPOR
308 # pragma config ALTI2C1 = ON // Alternate I2C1 pins (I2C1 mapped to ASDA1/ASCL1 pins)
309 # pragma config ALTI2C2 = OFF // Alternate I2C2 pins (I2C2 mapped to SDA2/SCL2 pins)
310 # pragma config WDTWIN = WIN25 // Watchdog Window Select bits (WDT Window is 25% of WDT period)
311 
312 // FWDT
313 # pragma config WDTPOST = PS512 // Watchdog Timer Postscaler bits (1:512)
314 # pragma config WDTPRE = PR128 // Watchdog Timer Prescaler bit (1:128)
315 # pragma config PLLKEN = ON // PLL Lock Enable bit (Clock switch to PLL source will wait until the PLL lock signal is valid.)
316 # pragma config WINDIS = OFF // Watchdog Timer Window Enable bit (Watchdog Timer in Non-Window mode)
317 # pragma config FWDTEN = OFF // Watchdog Timer Enable bit (Watchdog timer enabled/disabled by user software)
318 
319 // FOSC
320 # pragma config IOL1WAY = OFF // Peripheral pin select configuration (Allow multiple reconfigurations)
321 # pragma config FCKSM = CSECMD // Clock Switching Mode bits (Clock switching is enabled,Fail-safe Clock Monitor is disabled)
322 // FOSCSEL
323 # pragma config IESO = OFF // Two-speed Oscillator Start-up Enable bit (Start up with user-selected oscillator source)
324 // FGS
325 # pragma config GWRP = OFF // General Segment Write-Protect bit (General Segment may be written)
326 # pragma config GCP = OFF // General Segment Code-Protect bit (General Segment Code protect is Disabled)
327 ///\cond doxygen_ignore
328 # define CONFIG_BITS_DEFINED
329 ///\endcond
330 #endif // #ifdefined (__dsPIC33EP128GP502__) || (__dsPIC33EP128GP504__)
331 
332 #if defined(__dsPIC33EP512GP806__)
333 // DSPIC33EP512GP806 Configuration Bit Settings
334 // FICD
335 # pragma config ICS = PGD1 // ICD Communication Channel Select bits (Communicate on PGEC1 and PGED1)
336 # pragma config JTAGEN = OFF // JTAG Enable bit (JTAG is disabled)
337 
338 // FPOR
339 # pragma config ALTI2C1 = OFF // Alternate I2C1 pins (I2C1 mapped to SDA1/SCL1 pins)
340 # pragma config BOREN = ON // BROWN-OUT RESET DETECTION MUST BE ENABLED (per datasheet DS70616G p.479)
341 # pragma config FPWRT = PWR1 // POWER ON RESET TIMER DISABLED?
342 
343 // FWDT
344 # pragma config WDTPOST = PS512 // Watchdog Timer Postscaler bits (1:512)
345 # pragma config WDTPRE = PR128 // Watchdog Timer Prescaler bit (1:128)
346 # pragma config PLLKEN = ON // PLL Lock Enable bit (Clock switch to PLL source will wait until the PLL lock signal is valid.)
347 # pragma config WINDIS = OFF // Watchdog Timer Window Enable bit (Watchdog Timer in Non-Window mode)
348 # pragma config FWDTEN = OFF // Watchdog Timer Enable bit (Watchdog timer enabled/disabled by user software)
349 
350 // FOSC
351 # pragma config IOL1WAY = OFF // Peripheral pin select configuration (Allow multiple reconfigurations)
352 # pragma config FCKSM = CSECMD // Clock Switching Mode bits (Clock switching is enabled,Fail-safe Clock Monitor is disabled)
353 
354 // FOSCSEL
355 # pragma config IESO = OFF // Two-speed Oscillator Start-up Enable bit (Start up with user-selected oscillator source)
356 
357 // FGS
358 # pragma config GWRP = OFF // General Segment Write-Protect bit (General Segment may be written)
359 # pragma config GSS = OFF // General Segment Code-Protect bit (General Segment Code protect is Disabled)
360 # pragma config GSSK = OFF // General Segment KEY bit (General Segment protect is Disabled)
361 
362 # define CONFIG_BITS_DEFINED
363 ///\endcond
364 #endif // #ifdefined (__dsPIC33EP512GP806__)
365 
366 
367 #if defined(__PIC24HJ128GP502__)
368 
369 // FBS
370 # pragma config BWRP = WRPROTECT_OFF // Boot Segment Write Protect (Boot Segment may be written)
371 # pragma config BSS = NO_FLASH // Boot Segment Program Flash Code Protection (No Boot program Flash segment)
372 # pragma config RBS = NO_RAM // Boot Segment RAM Protection (No Boot RAM)
373 
374 // FSS
375 # pragma config SWRP = WRPROTECT_OFF // Secure Segment Program Write Protect (Secure segment may be written)
376 # pragma config SSS = NO_FLASH // Secure Segment Program Flash Code Protection (No Secure Segment)
377 # pragma config RSS = NO_RAM // Secure Segment Data RAM Protection (No Secure RAM)
378 
379 // FGS
380 # pragma config GWRP = OFF // General Code Segment Write Protect (User program memory is not write-protected)
381 # pragma config GSS = OFF // General Segment Code Protection (User program memory is not code-protected)
382 
383 // FOSCSEL
384 # pragma config IESO = OFF // Internal External Switch Over Mode (Start-up device with user-selected oscillator source)
385 
386 // FOSC
387 # pragma config IOL1WAY = OFF // Peripheral Pin Select Configuration (Allow Multiple Re-configurations)
388 # pragma config FCKSM = CSECMD // Clock Switching and Monitor (Clock switching is enabled, Fail-Safe Clock Monitor is disabled)
389 
390 // FWDT
391 # pragma config WDTPOST = PS512 // Watchdog Timer Postscaler (1:512)
392 # pragma config WDTPRE = PR128 // WDT Prescaler (1:128)
393 # pragma config WINDIS = OFF // Watchdog Timer Window (Watchdog Timer in Non-Window mode)
394 # pragma config FWDTEN = OFF // Watchdog Timer Enable (Watchdog timer enabled/disabled by user software)
395 
396 // FPOR
397 # pragma config FPWRT = PWR128 // POR Timer Value (128ms)
398 # pragma config ALTI2C = OFF // Alternate I2C pins (I2C mapped to SDA1/SCL1 pins)
399 
400 // FICD
401 # pragma config ICS = PGD1 // Comm Channel Select (Communicate on PGC1/EMUC1 and PGD1/EMUD1)
402 # pragma config JTAGEN = OFF // JTAG Port Enable (JTAG is Disabled)
403 
404 ///\cond doxygen_ignore
405 # define CONFIG_BITS_DEFINED
406 ///\endcond
407 #endif
408 
409 
410 // *********
411 // New chips
412 // *********
413 // Add new chips here.
414 //
415 // If the chip currently in use has not be detected, the config bits
416 // may not have been setup properly, so issue a warning.
417 // Other chips can be added to this file as needed.
418 #ifndef CONFIG_BITS_DEFINED
419 # warning "Edit common/pic24_configbits.c to add config bits for your processor!"
420 #endif
pic24_clockfreq.h
Configures the system clock.
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