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pic24_ecan.h
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1 /*
2  * "Copyright (c) 2008 Robert B. Reese, Bryan A. Jones, J. W. Bruce ("AUTHORS")"
3  * All rights reserved.
4  * (R. Reese, reese_AT_ece.msstate.edu, Mississippi State University)
5  * (B. A. Jones, bjones_AT_ece.msstate.edu, Mississippi State University)
6  * (J. W. Bruce, jwbruce_AT_ece.msstate.edu, Mississippi State University)
7  *
8  * Permission to use, copy, modify, and distribute this software and its
9  * documentation for any purpose, without fee, and without written agreement is
10  * hereby granted, provided that the above copyright notice, the following
11  * two paragraphs and the authors appear in all copies of this software.
12  *
13  * IN NO EVENT SHALL THE "AUTHORS" BE LIABLE TO ANY PARTY FOR
14  * DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT
15  * OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE "AUTHORS"
16  * HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
17  *
18  * THE "AUTHORS" SPECIFICALLY DISCLAIMS ANY WARRANTIES,
19  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
20  * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS
21  * ON AN "AS IS" BASIS, AND THE "AUTHORS" HAS NO OBLIGATION TO
22  * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS."
23  *
24  * Please maintain this header in its entirety when copying/modifying
25  * these files.
26  *
27  *
28  */
29 
30 #ifndef _PIC24_ECAN1_H_
31 #define _PIC24_ECAN1_H_
32 
33 #include <stdint.h>
34 #include "pic24_generic.h"
35 #include "pic24_chip.h"
36 
37 // Only include if this ECAN Module exists.
38 #if (NUM_ECAN_MODS >= 1)
39 
40 // Documentation for this file. If the \file tag isn't present,
41 // this file won't be documented.
42 // Note: place this comment below the #if NUM_ECAN_MODS so Doxygen
43 // will only see it once.
44 /** \file
45 * ECAN Header File
46 */
47 
48 #ifndef ECAN_1TIME_HEADER_DEFS
49 
50 #define ECAN_MODE_NORMAL 0
51 #define ECAN_MODE_DISABLED 1
52 #define ECAN_MODE_LOOPBACK 2
53 #define ECAN_MODE_LISTEN_ONLY 3
54 #define ECAN_MODE_CONFIGURE 4
55 #define ECAN_LISTEN_ALL_MESSAGES 7
56 
57 #define ECAN_FCAN_IS_FCY 1
58 #define ECAN_FCAN_IS_OSC 0
59 
60 
61 //CiCFG2 register (Baud rate config 2 register)
62 #define ECAN_NO_WAKEUP 0x4000
63 #define ECAN_SEG2PH_8TQ (0x0007 << 8)
64 #define ECAN_SEG2PH_7TQ (0x0006 << 8)
65 #define ECAN_SEG2PH_6TQ (0x0005 << 8)
66 #define ECAN_SEG2PH_5TQ (0x0004 << 8)
67 #define ECAN_SEG2PH_4TQ (0x0003 << 8)
68 #define ECAN_SEG2PH_3TQ (0x0002 << 8)
69 #define ECAN_SEG2PH_2TQ (0x0001 << 8)
70 #define ECAN_SEG2PH_1TQ (0x0000 << 8)
71 
72 #define ECAN_SEG2_PROGRAMMABLE 0x0080
73 #define ECAN_SEG2_FIXED 0x0000
74 
75 #define ECAN_SAMPLE_3TIMES 0x0040
76 #define ECAN_SAMPLE_1TIMES 0x0000
77 
78 #define ECAN_SEG1PH_8TQ (0x0007 << 3)
79 #define ECAN_SEG1PH_7TQ (0x0006 << 3)
80 #define ECAN_SEG1PH_6TQ (0x0005 << 3)
81 #define ECAN_SEG1PH_5TQ (0x0004 << 3)
82 #define ECAN_SEG1PH_4TQ (0x0003 << 3)
83 #define ECAN_SEG1PH_3TQ (0x0002 << 3)
84 #define ECAN_SEG1PH_2TQ (0x0001 << 3)
85 #define ECAN_SEG1PH_1TQ (0x0000 << 3)
86 
87 #define ECAN_PRSEG_8TQ 0x0007
88 #define ECAN_PRSEG_7TQ 0x0006
89 #define ECAN_PRSEG_6TQ 0x0005
90 #define ECAN_PRSEG_5TQ 0x0004
91 #define ECAN_PRSEG_4TQ 0x0003
92 #define ECAN_PRSEG_3TQ 0x0002
93 #define ECAN_PRSEG_2TQ 0x0001
94 #define ECAN_PRSEG_1TQ 0x0000
95 
96 //CiCFG1 register (Baud rate config 1 register)
97 #define ECAN_SYNC_JUMP_4 (0x0003 << 6)
98 #define ECAN_SYNC_JUMP_3 (0x0002 << 6)
99 #define ECAN_SYNC_JUMP_2 (0x0001 << 6)
100 #define ECAN_SYNC_JUMP_1 (0x0000 << 6)
101 
102 #define ECAN_PRE_2x64 0x003f
103 #define ECAN_PRE_2x63 0x003e
104 #define ECAN_PRE_2x62 0x003d
105 #define ECAN_PRE_2x61 0x003c
106 #define ECAN_PRE_2x60 0x003b
107 #define ECAN_PRE_2x59 0x003a
108 #define ECAN_PRE_2x58 0x0039
109 #define ECAN_PRE_2x57 0x0038
110 #define ECAN_PRE_2x56 0x0037
111 #define ECAN_PRE_2x55 0x0036
112 #define ECAN_PRE_2x54 0x0035
113 #define ECAN_PRE_2x53 0x0034
114 #define ECAN_PRE_2x52 0x0033
115 #define ECAN_PRE_2x51 0x0032
116 #define ECAN_PRE_2x50 0x0031
117 #define ECAN_PRE_2x49 0x0030
118 #define ECAN_PRE_2x48 0x002f
119 #define ECAN_PRE_2x47 0x002e
120 #define ECAN_PRE_2x46 0x002d
121 #define ECAN_PRE_2x45 0x002c
122 #define ECAN_PRE_2x44 0x002b
123 #define ECAN_PRE_2x43 0x002a
124 #define ECAN_PRE_2x42 0x0029
125 #define ECAN_PRE_2x41 0x0028
126 #define ECAN_PRE_2x40 0x0027
127 #define ECAN_PRE_2x39 0x0026
128 #define ECAN_PRE_2x38 0x0025
129 #define ECAN_PRE_2x37 0x0024
130 #define ECAN_PRE_2x36 0x0023
131 #define ECAN_PRE_2x35 0x0022
132 #define ECAN_PRE_2x34 0x0021
133 #define ECAN_PRE_2x33 0x0020
134 #define ECAN_PRE_2x32 0x001f
135 #define ECAN_PRE_2x31 0x001e
136 #define ECAN_PRE_2x30 0x001d
137 #define ECAN_PRE_2x29 0x001c
138 #define ECAN_PRE_2x28 0x001b
139 #define ECAN_PRE_2x27 0x001a
140 #define ECAN_PRE_2x26 0x0019
141 #define ECAN_PRE_2x25 0x0018
142 #define ECAN_PRE_2x24 0x0017
143 #define ECAN_PRE_2x23 0x0016
144 #define ECAN_PRE_2x22 0x0015
145 #define ECAN_PRE_2x21 0x0014
146 #define ECAN_PRE_2x20 0x0013
147 #define ECAN_PRE_2x19 0x0012
148 #define ECAN_PRE_2x18 0x0011
149 #define ECAN_PRE_2x17 0x0010
150 #define ECAN_PRE_2x16 0x000f
151 #define ECAN_PRE_2x15 0x000e
152 #define ECAN_PRE_2x14 0x000d
153 #define ECAN_PRE_2x13 0x000c
154 #define ECAN_PRE_2x12 0x000b
155 #define ECAN_PRE_2x11 0x000a
156 #define ECAN_PRE_2x10 0x0009
157 #define ECAN_PRE_2x9 0x0008
158 #define ECAN_PRE_2x8 0x0007
159 #define ECAN_PRE_2x7 0x0006
160 #define ECAN_PRE_2x6 0x0005
161 #define ECAN_PRE_2x5 0x0004
162 #define ECAN_PRE_2x4 0x0003
163 #define ECAN_PRE_2x3 0x0002
164 #define ECAN_PRE_2x2 0x0001
165 #define ECAN_PRE_2x1 0x0000
166 
167 //CiFCTRL register (FIFO Control register)
168 #define ECAN_DMA_BUF_SIZE_32 (0x0006 << 13)
169 #define ECAN_DMA_BUF_SIZE_24 (0x0005 << 13)
170 #define ECAN_DMA_BUF_SIZE_16 (0x0004 << 13)
171 #define ECAN_DMA_BUF_SIZE_12 (0x0003 << 13)
172 #define ECAN_DMA_BUF_SIZE_8 (0x0002 << 13)
173 #define ECAN_DMA_BUF_SIZE_6 (0x0001 << 13)
174 #define ECAN_DMA_BUF_SIZE_4 (0x0000 << 13)
175 
176 
177 #define ECAN_FIFO_START_AREA_31 31
178 #define ECAN_FIFO_START_AREA_30 30
179 #define ECAN_FIFO_START_AREA_29 29
180 #define ECAN_FIFO_START_AREA_28 28
181 #define ECAN_FIFO_START_AREA_27 27
182 #define ECAN_FIFO_START_AREA_26 26
183 #define ECAN_FIFO_START_AREA_25 25
184 #define ECAN_FIFO_START_AREA_24 24
185 #define ECAN_FIFO_START_AREA_23 23
186 #define ECAN_FIFO_START_AREA_22 22
187 #define ECAN_FIFO_START_AREA_21 21
188 #define ECAN_FIFO_START_AREA_20 20
189 #define ECAN_FIFO_START_AREA_19 19
190 #define ECAN_FIFO_START_AREA_18 18
191 #define ECAN_FIFO_START_AREA_17 17
192 #define ECAN_FIFO_START_AREA_16 16
193 #define ECAN_FIFO_START_AREA_15 15
194 #define ECAN_FIFO_START_AREA_14 14
195 #define ECAN_FIFO_START_AREA_13 13
196 #define ECAN_FIFO_START_AREA_12 12
197 #define ECAN_FIFO_START_AREA_11 11
198 #define ECAN_FIFO_START_AREA_10 10
199 #define ECAN_FIFO_START_AREA_9 9
200 #define ECAN_FIFO_START_AREA_8 8
201 #define ECAN_FIFO_START_AREA_7 7
202 #define ECAN_FIFO_START_AREA_6 6
203 #define ECAN_FIFO_START_AREA_5 5
204 #define ECAN_FIFO_START_AREA_4 4
205 #define ECAN_FIFO_START_AREA_3 3
206 #define ECAN_FIFO_START_AREA_2 2
207 #define ECAN_FIFO_START_AREA_1 1
208 #define ECAN_FIFO_START_AREA_0 0
209 
210 //CiRXFnSID register
211 #define ECAN_MATCH_EID 0x0008
212 #define ECAN_MATCH_SID 0x0000
213 
214 #define ECAN_USE_FIFO 0xF
215 
216 //CiTRmnCON TXRX buffer control
217 #define ECAN_RX_BUFF 0
218 #define ECAN_TX_BUFF 1
219 
220 
221 //Data structure for ECAN Data Frame
222 typedef struct _ECANW0 {
223  unsigned IDE: 1;
224  unsigned SRR:1;
225  unsigned SID:11;
226 } ECANW0;
227 typedef struct _ECANW1 {
228  unsigned EID17_6: 12;
229 } ECANW1;
230 
231 typedef struct _ECANW2 {
232  unsigned DLC:4;
233  unsigned RB0:1;
234  unsigned :3;
235  unsigned RB1:1;
236  unsigned RTR:1;
237  unsigned EID5_0:6;
238 } ECANW2;
239 
240 typedef struct _ECANW7 {
241  unsigned :8;
242  unsigned FILHIT:5;
243  unsigned :3;
244 } ECANW7;
245 
246 
247 
248 typedef struct _ECANMSG {
249  ECANW0 w0;
250  ECANW1 w1;
251  ECANW2 w2;
252  union64 data;
253  ECANW7 w7;
254 } ECANMSG;
255 
256 
257 void formatStandardDataFrameECAN (ECANMSG* p_ecanmsg, uint16_t u16_id, uint8_t u8_len);
258 void formatExtendedDataFrameECAN (ECANMSG* p_ecanmsg, uint32_t u32_id, uint8_t u8_len);
259 uint32_t getIdExtendedDataFrameECAN (ECANMSG* p_ecanmsg);
260 
261 #define ECAN_1TIME_HEADER_DEFS
262 #endif
263 
264 
265 
266 
267 #ifdef _C1IF
268 /** Waits until all characters placed in the UART have been sent. */
269 inline static void CHANGE_MODE_ECAN1(mode) {
270  C1CTRL1bits.REQOP = mode;
271  while(C1CTRL1bits.OPMODE != mode);
272 }
273 
274 /** Return the number (0-31) of the next ECAN FIFO read buffer
275  */
276 #define GET_FIFO_READBUFFER_ECAN1() (C1FIFO & 0x1F)
277 
278 void clrRxFullFlagECAN1(uint8_t u8_bufNum);
280 void clrRxFullOvfFlagsECAN1(void);
281 void configTxRxBufferECAN1(uint8_t u8_bufNum, uint8_t u8_type, uint8_t u8_priority);
282 void configRxFilterECAN1(uint8_t u8_filtNum, uint32_t u32_id, uint8_t u8_idType, uint8_t u8_bufnum, uint8_t u8_maskReg);
283 void configRxMaskECAN1(uint8_t u8_maskNum, uint32_t u32_idMask, uint8_t u8_idType, uint8_t u8_matchType);
284 void startTxECAN1(uint8_t u8_bufNum);
286 
287 #endif
288 
289 
290 #endif // #if (NUM_ECAN_MODS >= 1)
291 #endif // #define _PIC24_ECAN1_H_
292 
293 
294 
295 /*
296  * "Copyright (c) 2008 Robert B. Reese, Bryan A. Jones, J. W. Bruce ("AUTHORS")"
297  * All rights reserved.
298  * (R. Reese, reese_AT_ece.msstate.edu, Mississippi State University)
299  * (B. A. Jones, bjones_AT_ece.msstate.edu, Mississippi State University)
300  * (J. W. Bruce, jwbruce_AT_ece.msstate.edu, Mississippi State University)
301  *
302  * Permission to use, copy, modify, and distribute this software and its
303  * documentation for any purpose, without fee, and without written agreement is
304  * hereby granted, provided that the above copyright notice, the following
305  * two paragraphs and the authors appear in all copies of this software.
306  *
307  * IN NO EVENT SHALL THE "AUTHORS" BE LIABLE TO ANY PARTY FOR
308  * DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT
309  * OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE "AUTHORS"
310  * HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
311  *
312  * THE "AUTHORS" SPECIFICALLY DISCLAIMS ANY WARRANTIES,
313  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
314  * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS
315  * ON AN "AS IS" BASIS, AND THE "AUTHORS" HAS NO OBLIGATION TO
316  * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS."
317  *
318  * Please maintain this header in its entirety when copying/modifying
319  * these files.
320  *
321  *
322  */
323 
324 #ifndef _PIC24_ECAN2_H_
325 #define _PIC24_ECAN2_H_
326 
327 #include <stdint.h>
328 #include "pic24_generic.h"
329 #include "pic24_chip.h"
330 
331 // Only include if this ECAN Module exists.
332 #if (NUM_ECAN_MODS >= 2)
333 
334 // Documentation for this file. If the \file tag isn't present,
335 // this file won't be documented.
336 // Note: place this comment below the #if NUM_ECAN_MODS so Doxygen
337 // will only see it once.
338 /** \file
339 * ECAN Header File
340 */
341 
342 #ifndef ECAN_1TIME_HEADER_DEFS
343 
344 #define ECAN_MODE_NORMAL 0
345 #define ECAN_MODE_DISABLED 1
346 #define ECAN_MODE_LOOPBACK 2
347 #define ECAN_MODE_LISTEN_ONLY 3
348 #define ECAN_MODE_CONFIGURE 4
349 #define ECAN_LISTEN_ALL_MESSAGES 7
350 
351 #define ECAN_FCAN_IS_FCY 1
352 #define ECAN_FCAN_IS_OSC 0
353 
354 
355 //CiCFG2 register (Baud rate config 2 register)
356 #define ECAN_NO_WAKEUP 0x4000
357 #define ECAN_SEG2PH_8TQ (0x0007 << 8)
358 #define ECAN_SEG2PH_7TQ (0x0006 << 8)
359 #define ECAN_SEG2PH_6TQ (0x0005 << 8)
360 #define ECAN_SEG2PH_5TQ (0x0004 << 8)
361 #define ECAN_SEG2PH_4TQ (0x0003 << 8)
362 #define ECAN_SEG2PH_3TQ (0x0002 << 8)
363 #define ECAN_SEG2PH_2TQ (0x0001 << 8)
364 #define ECAN_SEG2PH_1TQ (0x0000 << 8)
365 
366 #define ECAN_SEG2_PROGRAMMABLE 0x0080
367 #define ECAN_SEG2_FIXED 0x0000
368 
369 #define ECAN_SAMPLE_3TIMES 0x0040
370 #define ECAN_SAMPLE_1TIMES 0x0000
371 
372 #define ECAN_SEG1PH_8TQ (0x0007 << 3)
373 #define ECAN_SEG1PH_7TQ (0x0006 << 3)
374 #define ECAN_SEG1PH_6TQ (0x0005 << 3)
375 #define ECAN_SEG1PH_5TQ (0x0004 << 3)
376 #define ECAN_SEG1PH_4TQ (0x0003 << 3)
377 #define ECAN_SEG1PH_3TQ (0x0002 << 3)
378 #define ECAN_SEG1PH_2TQ (0x0001 << 3)
379 #define ECAN_SEG1PH_1TQ (0x0000 << 3)
380 
381 #define ECAN_PRSEG_8TQ 0x0007
382 #define ECAN_PRSEG_7TQ 0x0006
383 #define ECAN_PRSEG_6TQ 0x0005
384 #define ECAN_PRSEG_5TQ 0x0004
385 #define ECAN_PRSEG_4TQ 0x0003
386 #define ECAN_PRSEG_3TQ 0x0002
387 #define ECAN_PRSEG_2TQ 0x0001
388 #define ECAN_PRSEG_1TQ 0x0000
389 
390 //CiCFG1 register (Baud rate config 1 register)
391 #define ECAN_SYNC_JUMP_4 (0x0003 << 6)
392 #define ECAN_SYNC_JUMP_3 (0x0002 << 6)
393 #define ECAN_SYNC_JUMP_2 (0x0001 << 6)
394 #define ECAN_SYNC_JUMP_1 (0x0000 << 6)
395 
396 #define ECAN_PRE_2x64 0x003f
397 #define ECAN_PRE_2x63 0x003e
398 #define ECAN_PRE_2x62 0x003d
399 #define ECAN_PRE_2x61 0x003c
400 #define ECAN_PRE_2x60 0x003b
401 #define ECAN_PRE_2x59 0x003a
402 #define ECAN_PRE_2x58 0x0039
403 #define ECAN_PRE_2x57 0x0038
404 #define ECAN_PRE_2x56 0x0037
405 #define ECAN_PRE_2x55 0x0036
406 #define ECAN_PRE_2x54 0x0035
407 #define ECAN_PRE_2x53 0x0034
408 #define ECAN_PRE_2x52 0x0033
409 #define ECAN_PRE_2x51 0x0032
410 #define ECAN_PRE_2x50 0x0031
411 #define ECAN_PRE_2x49 0x0030
412 #define ECAN_PRE_2x48 0x002f
413 #define ECAN_PRE_2x47 0x002e
414 #define ECAN_PRE_2x46 0x002d
415 #define ECAN_PRE_2x45 0x002c
416 #define ECAN_PRE_2x44 0x002b
417 #define ECAN_PRE_2x43 0x002a
418 #define ECAN_PRE_2x42 0x0029
419 #define ECAN_PRE_2x41 0x0028
420 #define ECAN_PRE_2x40 0x0027
421 #define ECAN_PRE_2x39 0x0026
422 #define ECAN_PRE_2x38 0x0025
423 #define ECAN_PRE_2x37 0x0024
424 #define ECAN_PRE_2x36 0x0023
425 #define ECAN_PRE_2x35 0x0022
426 #define ECAN_PRE_2x34 0x0021
427 #define ECAN_PRE_2x33 0x0020
428 #define ECAN_PRE_2x32 0x001f
429 #define ECAN_PRE_2x31 0x001e
430 #define ECAN_PRE_2x30 0x001d
431 #define ECAN_PRE_2x29 0x001c
432 #define ECAN_PRE_2x28 0x001b
433 #define ECAN_PRE_2x27 0x001a
434 #define ECAN_PRE_2x26 0x0019
435 #define ECAN_PRE_2x25 0x0018
436 #define ECAN_PRE_2x24 0x0017
437 #define ECAN_PRE_2x23 0x0016
438 #define ECAN_PRE_2x22 0x0015
439 #define ECAN_PRE_2x21 0x0014
440 #define ECAN_PRE_2x20 0x0013
441 #define ECAN_PRE_2x19 0x0012
442 #define ECAN_PRE_2x18 0x0011
443 #define ECAN_PRE_2x17 0x0010
444 #define ECAN_PRE_2x16 0x000f
445 #define ECAN_PRE_2x15 0x000e
446 #define ECAN_PRE_2x14 0x000d
447 #define ECAN_PRE_2x13 0x000c
448 #define ECAN_PRE_2x12 0x000b
449 #define ECAN_PRE_2x11 0x000a
450 #define ECAN_PRE_2x10 0x0009
451 #define ECAN_PRE_2x9 0x0008
452 #define ECAN_PRE_2x8 0x0007
453 #define ECAN_PRE_2x7 0x0006
454 #define ECAN_PRE_2x6 0x0005
455 #define ECAN_PRE_2x5 0x0004
456 #define ECAN_PRE_2x4 0x0003
457 #define ECAN_PRE_2x3 0x0002
458 #define ECAN_PRE_2x2 0x0001
459 #define ECAN_PRE_2x1 0x0000
460 
461 //CiFCTRL register (FIFO Control register)
462 #define ECAN_DMA_BUF_SIZE_32 (0x0006 << 13)
463 #define ECAN_DMA_BUF_SIZE_24 (0x0005 << 13)
464 #define ECAN_DMA_BUF_SIZE_16 (0x0004 << 13)
465 #define ECAN_DMA_BUF_SIZE_12 (0x0003 << 13)
466 #define ECAN_DMA_BUF_SIZE_8 (0x0002 << 13)
467 #define ECAN_DMA_BUF_SIZE_6 (0x0001 << 13)
468 #define ECAN_DMA_BUF_SIZE_4 (0x0000 << 13)
469 
470 
471 #define ECAN_FIFO_START_AREA_31 31
472 #define ECAN_FIFO_START_AREA_30 30
473 #define ECAN_FIFO_START_AREA_29 29
474 #define ECAN_FIFO_START_AREA_28 28
475 #define ECAN_FIFO_START_AREA_27 27
476 #define ECAN_FIFO_START_AREA_26 26
477 #define ECAN_FIFO_START_AREA_25 25
478 #define ECAN_FIFO_START_AREA_24 24
479 #define ECAN_FIFO_START_AREA_23 23
480 #define ECAN_FIFO_START_AREA_22 22
481 #define ECAN_FIFO_START_AREA_21 21
482 #define ECAN_FIFO_START_AREA_20 20
483 #define ECAN_FIFO_START_AREA_19 19
484 #define ECAN_FIFO_START_AREA_18 18
485 #define ECAN_FIFO_START_AREA_17 17
486 #define ECAN_FIFO_START_AREA_16 16
487 #define ECAN_FIFO_START_AREA_15 15
488 #define ECAN_FIFO_START_AREA_14 14
489 #define ECAN_FIFO_START_AREA_13 13
490 #define ECAN_FIFO_START_AREA_12 12
491 #define ECAN_FIFO_START_AREA_11 11
492 #define ECAN_FIFO_START_AREA_10 10
493 #define ECAN_FIFO_START_AREA_9 9
494 #define ECAN_FIFO_START_AREA_8 8
495 #define ECAN_FIFO_START_AREA_7 7
496 #define ECAN_FIFO_START_AREA_6 6
497 #define ECAN_FIFO_START_AREA_5 5
498 #define ECAN_FIFO_START_AREA_4 4
499 #define ECAN_FIFO_START_AREA_3 3
500 #define ECAN_FIFO_START_AREA_2 2
501 #define ECAN_FIFO_START_AREA_1 1
502 #define ECAN_FIFO_START_AREA_0 0
503 
504 //CiRXFnSID register
505 #define ECAN_MATCH_EID 0x0008
506 #define ECAN_MATCH_SID 0x0000
507 
508 #define ECAN_USE_FIFO 0xF
509 
510 //CiTRmnCON TXRX buffer control
511 #define ECAN_RX_BUFF 0
512 #define ECAN_TX_BUFF 1
513 
514 
515 //Data structure for ECAN Data Frame
516 typedef struct _ECANW0 {
517  unsigned IDE: 1;
518  unsigned SRR:1;
519  unsigned SID:11;
520 } ECANW0;
521 typedef struct _ECANW1 {
522  unsigned EID17_6: 12;
523 } ECANW1;
524 
525 typedef struct _ECANW2 {
526  unsigned DLC:4;
527  unsigned RB0:1;
528  unsigned :3;
529  unsigned RB1:1;
530  unsigned RTR:1;
531  unsigned EID5_0:6;
532 } ECANW2;
533 
534 typedef struct _ECANW7 {
535  unsigned :8;
536  unsigned FILHIT:5;
537  unsigned :3;
538 } ECANW7;
539 
540 
541 
542 typedef struct _ECANMSG {
543  ECANW0 w0;
544  ECANW1 w1;
545  ECANW2 w2;
546  union64 data;
547  ECANW7 w7;
548 } ECANMSG;
549 
550 
551 void formatStandardDataFrameECAN (ECANMSG* p_ecanmsg, uint16_t u16_id, uint8_t u8_len);
552 void formatExtendedDataFrameECAN (ECANMSG* p_ecanmsg, uint32_t u32_id, uint8_t u8_len);
553 uint32_t getIdExtendedDataFrameECAN (ECANMSG* p_ecanmsg);
554 
555 #define ECAN_1TIME_HEADER_DEFS
556 #endif
557 
558 
559 
560 
561 #ifdef _C2IF
562 /** Waits until all characters placed in the UART have been sent. */
563 inline static void CHANGE_MODE_ECAN2(mode) {
564  C2CTRL1bits.REQOP = mode;
565  while(C2CTRL1bits.OPMODE != mode);
566 }
567 
568 /** Return the number (0-31) of the next ECAN FIFO read buffer
569  */
570 #define GET_FIFO_READBUFFER_ECAN2() (C2FIFO & 0x1F)
571 
572 void clrRxFullFlagECAN2(uint8_t u8_bufNum);
573 uint8_t getRxFullFlagECAN2(uint8_t u8_bufNum);
574 void clrRxFullOvfFlagsECAN2(void);
575 void configTxRxBufferECAN2(uint8_t u8_bufNum, uint8_t u8_type, uint8_t u8_priority);
576 void configRxFilterECAN2(uint8_t u8_filtNum, uint32_t u32_id, uint8_t u8_idType, uint8_t u8_bufnum, uint8_t u8_maskReg);
577 void configRxMaskECAN2(uint8_t u8_maskNum, uint32_t u32_idMask, uint8_t u8_idType, uint8_t u8_matchType);
578 void startTxECAN2(uint8_t u8_bufNum);
579 uint8_t getTxInProgressECAN2(uint8_t u8_bufNum);
580 
581 #endif
582 
583 
584 #endif // #if (NUM_ECAN_MODS >= 2)
585 #endif // #define _PIC24_ECAN2_H_
586 
587 
588