72 #if !USE_CLOCK_TIMEOUT
74 void checkClockTimeout(
void) {
83 #define CLOCKTIMEOUT_MAX 200000L
84 #if ( defined(__PIC24H__) || defined(__dsPIC33F__) )
85 #define FRC_FCY 40000000L
86 #elif ( defined(__PIC24F__) || defined(__PIC24FK__) )
87 #define FRC_FCY 16000000L
88 #elif ( defined(__PIC24E__) || defined(__dsPIC33E__) )
89 #define FRC_FCY 60000000L
91 #error Unknown processor.
96 static void configFrcUART(
void) {
100 #if ( defined(__PIC24H__) || defined(__dsPIC33F__) )
101 configClockFRCPLL_FCY40MHz();
102 #elif ( defined(__PIC24E__) || defined(__dsPIC33E__) )
103 configClockFRCPLL_FCY60MHz();
104 #elif ( defined(__PIC24F__) || defined(__PIC24FK__) )
106 configClockFRCPLL_FCY16MHz();
108 #error Unknown processor
117 f_brg = (((float) FRC_FCY)/((float) DEFAULT_BAUDRATE)/4.0) - 1.0;
121 #if (NUM_UART_MODS >= 1)
124 U1MODEbits.BRGH = FRC_BRGH;
127 #if (NUM_UART_MODS >= 2)
130 U2MODEbits.BRGH = FRC_BRGH;
133 #if (NUM_UART_MODS >= 3)
136 U3MODEbits.BRGH = FRC_BRGH;
139 #if (NUM_UART_MODS >= 4)
142 U4MODEbits.BRGH = FRC_BRGH;
150 static void checkClockTimeout(
void) {
151 static uint32_t u32_timeoutCount = 0;
156 if (u32_timeoutCount == 0xFFFFFFFF)
return;
161 if (u32_timeoutCount < CLOCKTIMEOUT_MAX)
return;
164 u32_timeoutCount = 0xFFFFFFFF;
168 "Your clock choice failed to initialize, have switched to internal Fast RC oscillator +PLL.\n"
169 "Check your setting for the 'CLOCK_CONFIG' macro.\n"
170 "Watch the compiler output window when pic24_clockfreq.c is compiled, a warning message\n"
171 "will tell you the selected value for 'CLOCK_CONFIG'.\n"
172 "In MPLAB, use Project->Build Options->Project, then click on MPLAB C30 tab to see if \n"
173 "the macro is defined there. If the macro is selecting an external crystal (the primary oscillator),\n"
174 "and your board does not have a crystal, you will get this message.\n"
175 "Delete the macro definition from the MPLAB project if you want to use the default \n"
176 "clock choice of FRC + PLL.\n"
177 "You must recompile and reprogram with an appropriate CLOCK_CONFIG choice for this code to execute.\n");
189 OSCCONBITS OSCCONBITS_copy;
202 OSCCONBITS_copy = OSCCONbits;
203 OSCCONBITS_copy.NOSC = u8_source;
204 OSCCONBITS_copy.OSWEN = 1;
206 __builtin_write_OSCCONH(
BITS2BYTEH(OSCCONBITS_copy));
208 __builtin_write_OSCCONL(
BITS2BYTEL(OSCCONBITS_copy));
216 while (_OSWEN == 1) {
230 while (_COSC != u8_source) checkClockTimeout();
234 #if IS_CLOCK_CONFIG(SIM_CLOCK)
235 #warning Clock configured for simulation, FCY = 1 Mhz
237 #if GET_IS_SUPPORTED(SIM_CLOCK)
238 void configClockSim(
void) { }
242 #if IS_CLOCK_CONFIG(FRCPLL_FCY16MHz)
243 #warning Clock configured for FRCPLL, FCY = 16 MHz
245 #if GET_IS_SUPPORTED(FRCPLL_FCY16MHz)
246 void configClockFRCPLL_FCY16MHz(
void) {
270 #elif defined(PLLDIV_NODIV)
271 #warning Ensure that the PLLDIV value is set to divide by 2 in the configuration bits for FRCPLL_FCY16MHz clock option!!
282 #if IS_CLOCK_CONFIG(FRC_FCY4MHz)
283 #warning Clock configured for FRC, FCY = 4 MHz.
284 #warning Baud rates of 19200 or lower recommended for this clock choice.
286 #if GET_IS_SUPPORTED(FRC_FCY4MHz)
287 void configClockFRC_FCY4MHz(
void) {
295 #if IS_CLOCK_CONFIG(PRI_NO_PLL_7372KHzCrystal)
296 #warning Clock configured for a 7.372 MHz crystal primary oscillator, no PLL
298 #if GET_IS_SUPPORTED(PRI_NO_PLL_7372KHzCrystal)
299 void configClockPRI_NO_PLL_7372KHzCrystal(
void) {
305 #if IS_CLOCK_CONFIG(FRC_FCY3685KHz)
306 #warning Clock configured for FRC, FCY = 3.685 MHz
307 #warning Baud rates of 9600 or lower recommended for this clock choice.
309 #if GET_IS_SUPPORTED(FRC_FCY3685KHz)
310 void configClockFRC_FCY3685KHz(
void) {
321 #if IS_CLOCK_CONFIG(FRCPLL_FCY40MHz)
322 #warning Clock configured for FRCPLL, FCY = 40 MHz
324 #if GET_IS_SUPPORTED(FRCPLL_FCY40MHz)
325 void configClockFRCPLL_FCY40MHz(
void) {
364 #if IS_CLOCK_CONFIG(FRCPLL_FCY60MHz)
365 #warning Clock configured for FRCPLL, FCY = 60 MHz
367 #if GET_IS_SUPPORTED(FRCPLL_FCY60MHz)
368 void configClockFRCPLL_FCY60MHz(
void) {
392 #if IS_CLOCK_CONFIG(FRCPLL_FCY70MHz)
393 #warning Clock configured for FRCPLL, FCY = 70 MHz
395 #if GET_IS_SUPPORTED(FRCPLL_FCY70MHz)
396 void configClockFRCPLL_FCY70MHz(
void) {
422 #if IS_CLOCK_CONFIG(PRIPLL_7372KHzCrystal_40MHzFCY)
423 #warning Clock configured for PRIPLL using a 7.3727 Mhz primary oscillator, FCY = 40 MHz
425 #if GET_IS_SUPPORTED(PRIPLL_7372KHzCrystal_40MHzFCY)
426 void configClockPRIPLL_7372KHzCrystal_40MHzFCY(
void) {
439 #if IS_CLOCK_CONFIG(PRIPLL_8MHzCrystal_40MHzFCY)
440 #warning Clock configured for PRIPLL using an 8.0 Mhz primary oscillator, FCY = 40 MHz
442 #if GET_IS_SUPPORTED(PRIPLL_8MHzCrystal_40MHzFCY)
443 void configClockPRIPLL_8MHzCrystal_40MHzFCY(
void) {
460 #if IS_CLOCK_CONFIG(PRIPLL_8MHzCrystal_16MHzFCY)
461 #warning Clock configured for PRIPLL using a 8.0 Mhz primary oscillator, FCY = 16 MHz
463 #if GET_IS_SUPPORTED(PRIPLL_8MHzCrystal_16MHzFCY)
464 void configClockPRIPLL_8MHzCrystal_16MHzFCY(
void) {
488 #elif defined(PLLDIV_NODIV)
489 #warning Ensure that the PLLDIV value is set to divide by 2 in the configuration bits for PRIPLL_8MHzCrystal_16MHzFCY clock option!!
500 #if IS_CLOCK_CONFIG(PRI_8MHzCrystal_4MHzFCY)
501 #warning Clock configured for PRI using a 8.0 Mhz primary oscillator, FCY = 4 MHz
503 #if GET_IS_SUPPORTED(PRI_8MHzCrystal_4MHzFCY)
504 void configClockPRI_8MHzCrystal_4MHzFCY(
void) {