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pic24_comparator.h
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1 /* Standard copyright does not go in this file because
2 * of the use of Microchip provided macros, see comments below.
3 */
4 // Documentation for this file. If the \file tag isn't present,
5 // this file won't be documented.
6 /** \file
7  * Macros to support comparator module configuration
8  */
9 
10 
11 #ifndef _PIC24_COMPARATOR_H_
12 #define _PIC24_COMPARATOR_H_
13 
14 /*
15  * Changes:
16  * 12/1/08 Fixed CMP1_POS_IP_VIN_POS definition
17  */
18 
19 
20 /*
21 The following macros are the AND/OR macros found in the
22 the MPLAB C30/src/peripheral_24F/comparator.h file and placed
23 in this header for use solely and exclusively on Microchip
24 PICmicro Microcontroller products as
25 specified in the MPLAB C30/src/peripheral_24F/comparator.h header.
26 
27 Changed the mixed case macros to all uppercase
28 
29 */
30 
31 /*Registers Defaults*/
32 #define COMP_CVRCON_VAL 0x0000
33 #define COMP_CMCON_VAL 0x0000
34 
35 #define CMP_IDLE_STOP 0x8000 /* When device enters Idle mode, module does notgenerate interrupts.Module is still enabled. */
36 #define CMP_IDLE_CON 0x0000 /* continue operation in idle mode */
37 #define CMP_IDLE_MASK (~CMP_IDLE_STOP)
38 
39 #define CMP2_CHANGE_STATE 0x2000 /* Comparator output changed states */
40 #define CMP2_NO_CHANGE 0x0000 /* Comparator output did not change states */
41 #define CMP2_STATE_MASK (~CMP2_CHANGE_STATE )
42 
43 #define CMP1_CHANGE_STATE 0x1000 /* Comparator output changed states */
44 #define CMP1_NO_CHANGE 0x0000 /* Comparator output did not change states */
45 #define CMP1_ENBL_DSBL_MASK (~CMP1_CHANGE_STATE )
46 
47 #define CMP2_ENABLE 0x0800 /* Comparator is enabled */
48 #define CMP2_DISABLE 0x0000 /* Comparator is disabled */
49 #define CMP2_ENBL_DSBL_MASK (~CMP2_ENABLE)
50 
51 #define CMP1_ENABLE 0x0400 /* Comparator is enabled */
52 #define CMP1_DISABLE 0x0000 /* Comparator is disabled */
53 #define CMP1_STATE_MASK (~CMP1_ENABLE)
54 
55 #define CMP2_OUTPUT_ENABLE 0x0200 /* Comparator output driven on the output pad */
56 #define CMP2_OUTPUT_DISABLE 0x0000 /* Comparator output is not driven on the output pad */
57 #define CMP2_OUTPUT_MASK (~CMP2_OUTPUT_ENABLE)
58 
59 #define CMP1_OUTPUT_ENABLE 0x0100 /* Comparator output driven on the output pad */
60 #define CMP1_OUTPUT_DISABLE 0x0000 /* Comparator output is not driven on the output pad */
61 #define CMP1_OUTPUT_MASK (~CMP1_OUTPUT_ENABLE)
62 
63 #define CMP2_INV_OUTPUT 0x0020 /* C2 output inverted */
64 #define CMP2_NORMAL_OUTPUT 0x0000 /* C2 output not inverted */
65 #define CMP2_INV_OUTPUT_MASK (~CMP2_INV_OUTPUT)
66 
67 #define CMP1_INV_OUTPUT 0x0010 /* C1 output inverted */
68 #define CMP1_NORMAL_OUTPUT 0x0000 /* C1 output not inverted */
69 #define CMP1_INV_OUTPUT_MASK (~CMP1_INV_OUTPUT)
70 
71 #define CMP2_NEG_IP_VIN_POS 0x0008 /* Input is connected to Vin+ */
72 #define CMP2_NEG_IP_VIN_NEG 0x0000 /* Input is connected to Vin- */
73 #define CMP2_NEG_IP_MASK (~CMP2_NEG_IP_VIN_POS)
74 
75 #define CMP2_POS_IP_VIN_POS 0x0004 /* Input is connected to Vin+ */
76 #define CMP2_POS_IP_CV_REF 0x0000 /* Input is connected to Vin- */
77 #define CMP2_POS_IP_MASK (~CMP2_POS_IP_VIN_POS)
78 
79 #define CMP1_NEG_IP_VIN_POS 0x0002 /* Input is connected to Vin+ */
80 #define CMP1_NEG_IP_VIN_NEG 0x0000 /* Input is connected to Vin- */
81 #define CMP1_NEG_IP_MASK (~CMP1_NEG_IP_VIN_POS)
82 
83 #define CMP1_POS_IP_VIN_POS 0x0001 /* Input is connected to Vin+ */
84 #define CMP1_POS_IP_CV_REF 0x0000 /* Input is connected to Vin- */
85 #define CMP1_POS_IP_MASK (~CMP1_POS_IP_VIN_POS)
86 
87 #define CMP_VREF_ENABLE 0x0080 /* CVREF circuit powered on */
88 #define CMP_VREF_DISABLE 0x0000 /* CVREF circuit powered down */
89 #define CMP1_VREF_MASK (~CMP_VREF_ENABLE)
90 
91 #define CMP_VREF_OUTPUT_ENABLE 0x0040 /* CVREF voltage level is output on CVREF pin */
92 #define CMP_VREF_OUTPUT_DISABLE 0x0000 /* CVREF voltage level is disconnected from CVREF pin */
93 #define CMP_VREF_OUTPUT_MASK (~CMP_VREF_OUTPUT_ENABLE)
94 
95 #define CMP_VREF_SELECT_24_STEPS 0x0020 /* 0 to 0.67 CVRSRC, with CVRSRC/24 step size */
96 #define CMP_VREF_SELECT_32_STEPS 0x0000 /* 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size */
97 #define CMP_VREF_STEP_SELECT_MASK (~CMP_VREF_SELECT_24_STEPS) /* 0 to 0.67 CVRSRC, with CVRSRC/24 step size */
98 
99 #define CMP_VRSRC_VREF_VREF 0x0010 /* Comparator reference source CVRSRC = VREF+ – VREF- */
100 #define CMP_VRSRC_AVDD_AVSS 0x0000 /* Comparator reference source CVRSRC = AVDD – AVSS */
101 #define CMP_VRSRC_MASK (~CMP_VRSRC_VREF_VREF)
102 
103 
104 #define CMP_0P0_CVRR_1 0x0020
105 #define CMP_0P04_CVRR_1 0x0021
106 #define CMP_0P08_CVRR_1 0x0022
107 #define CMP_0P12_CVRR_1 0x0023
108 #define CMP_0P16_CVRR_1 0x0024
109 #define CMP_0P20_CVRR_1 0x0025
110 #define CMP_0P25_CVRR_1 0x0026
111 #define CMP_0P29_CVRR_1 0x0027
112 #define CMP_0P33_CVRR_1 0x0028
113 #define CMP_0P37_CVRR_1 0x0029
114 #define CMP_0P41_CVRR_1 0x002A
115 #define CMP_0P45_CVRR_1 0x002B
116 #define CMP_0P50_CVRR_1 0x002C
117 #define CMP_0P54_CVRR_1 0x002D
118 #define CMP_0P58_CVRR_1 0x002E
119 #define CMP_0P62_CVRR_1 0x002F
120 
121 #define CMP_0P25_CVRR_0 0x0000
122 #define CMP_0P28_CVRR_0 0x0001
123 #define CMP_0P31_CVRR_0 0x0002
124 #define CMP_0P34_CVRR_0 0x0003
125 #define CMP_0P37_CVRR_0 0x0004
126 #define CMP_0P40_CVRR_0 0x0005
127 #define CMP_0P43_CVRR_0 0x0006
128 #define CMP_0P46_CVRR_0 0x0007
129 #define CMP_0P50_CVRR_0 0x0008
130 #define CMP_0P53_CVRR_0 0x0009
131 #define CMP_0P56_CVRR_0 0x000A
132 #define CMP_0P59_CVRR_0 0x000B
133 #define CMP_0P62_CVRR_0 0x000C
134 #define CMP_0P65_CVRR_0 0x000D
135 #define CMP_0P68_CVRR_0 0x000E
136 #define CMP_0P71_CVRR_0 0x000F
137 
138 
139 #endif