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pic24_adc.h
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1 /* Standard copyright does not go in this file because
2 * of the use of Microchip provided macros, see comments below.
3 */
4 // Documentation for this file. If the \file tag isn't present,
5 // this file won't be documented.
6 /** \file
7  * To do.
8  */
9 
10 #ifndef _PIC24_ADC_H_
11 #define _PIC24_ADC_H_
12 
13 #include <stdint.h>
14 #include "pic24_chip.h"
15 #include "pic24_util.h"
16 
17 /**
18  * Prototype PIC24_ADC library functions here
19  * (functions live in the common/pic24_adc.c file)
20  */
21 uint16_t convertADC1(void);
22 void configADC1_ManualCH0(uint16_t u16_Ch0PositiveMask, uint8_t u8_autoSampleTime, uint8_t u8_Use12bits);
23 void configADC1_AutoScanIrqCH0(uint16_t u16_ch0ScanMask, uint8_t u8_autoSampleTime, uint8_t u8_12bit);
24 void configADC1_AutoHalfScanIrqCH0(uint16_t u16_ch0ScanMask, uint8_t u8_autoSampleTime, uint8_t u8_12bit);
25 void configADC1_Simul4ChanIrq(uint8_t u8_ch0Select, uint16_t u16_ch123SelectMask, uint16_t u16_numTcyMask);
26 
27 /** Determines if the conversion on AD1 is done.
28  * Returns 1 if the conversion has completed, or 0 if the conversion
29  * has not started or is in progress.
30  * \return True (1) if the conversion has completed, 0 if not.
31  */
32 #define IS_CONVERSION_COMPLETE_ADC1() AD1CON1bits.DONE
33 
34 /** Waits until the conversion is completed. */
37  doHeartbeat();
38 }
39 
40 /** Determines if the AD1 sample-and-hold amplifier(s) are sampling.
41  * Returns 1 if the sample-and-hold amplifier(s) are sampling,
42  * or 0 if sample-and-hold amplifier(s) are holding.
43  * \return True (1) if the sample-and-hold amplifier(s) are sampling, 0 if not.
44  */
45 #define IS_SAMPLING_ADC1() AD1CON1bits.SAMP
46 #define SET_SAMP_BIT_ADC1() AD1CON1bits.SAMP=1
47 
48 /*
49 The following macros are a subset of the AND/OR macros found in the
50 the MPLAB C30/src/peripheral_24F/include/adc.h file and placed
51 in this header for use solely and exclusively on Microchip
52 PICmicro Microcontroller products as
53 specified in the MPLAB C30/src/peripheral_24F/include/adc.h header.
54 
55 Edits have been made in the comments to correct some
56 minor typos.
57 */
58 /* AD1CON1 Configuration Bit Definitions */
59 
60 #define ADC_MODULE_ON 0x8000 /* A/D Converter on */
61 #define ADC_MODULE_OFF 0x0000 /* A/D Converter off */
62 #define ADC_MODULE_MASK (~ADC_MODULE_ON)
63 
64 #define ADC_IDLE_CONTINUE 0x2000 /* A/D Operate in Idle mode */
65 #define ADC_IDLE_STOP 0x0000 /* A/D Stop in Idle mode */
66 #define ADC_IDLE_MASK (~ADC_IDLE_CONTINUE)
67 
68 #define ADC_ADDMABM_SCATTER 0x0000 /* DMA buffers are written in Scatter/Gather mode */
69 #define ADC_ADDMABM_ORDER 0x1000 /* DMA buffers are written in the order of conversion */
70 #define ADC_ADDMABM_MASK (~ADC_ADDMABM_ORDER)
71 
72 #define ADC_12BIT 0x0400 /* A/D conversion is 12bits instead of 10bits */
73 #define ADC_10BIT 0x0000 /* A/D conversion is normal 10bits */
74 
75 #define ADC_FORMAT_SIGN_FRACT 0x0300 /* A/D data format signed fractional */
76 #define ADC_FORMAT_FRACT 0x0200 /* A/D data format fractional */
77 #define ADC_FORMAT_SIGN_INT 0x0100 /* A/D data format signed integer */
78 #define ADC_FORMAT_INTG 0x0000 /* A/D data format integer */
79 #define ADC_FORMAT_MASK (~ADC_FORMAT_SIGN_FRACT)
80 
81 #define ADC_CLK_AUTO 0x00E0 /* Internal counter ends sampling and starts conversion (Auto convert) */
82 #define ADC_CLK_MPWM 0x0060 /* MPWM interval ends sampling and starts conversion */
83 #define ADC_CLK_TMR 0x0040 /* GP Timer compare ends sampling and starts conversion */
84 #define ADC_CLK_INT0 0x0020 /* Active transition on INTx ends sampling and starts conversion */
85 #define ADC_CLK_MANUAL 0x0000 /* Clearing sample (SAMP) bit ends sampling and starts conversion */
86 #define ADC_CLK_MASK (~ADC_CLK_AUTO)
87 
88 #define ADC_SAMPLE_SIMULTANEOUS 0x0008 /* 10bit Only: samples CH0/1 or CH0/1/2/3 simultaneously depending on ADxCON2.CHPS bits */
89 #define ADC_SAMPLE_INDIVIDUAL 0x0000 /* Samples channels sequentially */
90 
91 #define ADC_AUTO_SAMPLING_ON 0x0004 /* Sampling begins immediately after last conversion */
92 #define ADC_AUTO_SAMPLING_OFF 0x0000 /* Sampling begins when SAMP bit is set */
93 #define ADC_AUTO_SAMPLING_MASK (~ADC_AUTO_SAMPLING_ON)
94 
95 #define ADC_SAMP_ON 0x0002 /* sample / hold amplifiers are sampling */
96 #define ADC_SAMP_OFF 0x0000 /* sample / hold amplifiers are holding */
97 #define ADC_SAMP_MASK (~ADC_SAMP_ON)
98 
99 
100 /* defines for the ADCON2 register */
101 #define ADC_VREF_EXT_AVSS 0x2000 /* A/D Voltage reference configuration Vref+ external and Vref- is AVss */
102 #define ADC_VREF_AVDD_EXT 0x4000 /* A/D Voltage reference configuration Vref+ AVdd and Vref- external */
103 #define ADC_VREF_EXT_EXT 0x6000 /* A/D Voltage reference configuration both Vref+ and Vref- are external */
104 #define ADC_VREF_AVDD_AVSS 0x8000 /* A/D Voltage reference configuration Vref+ is AVdd and Vref- is AVss */
105 #define ADC_VREF_MASK (~(ADC_VREF_AVDD_AVSS | ADC_VREF_EXT_EXT))/* A/D Voltage reference configuration Vref+ is AVdd and Vref- is AVss */
106 
107 #define ADC_SCAN_ON 0x0400 /* A/D Scan Input Selections for CH0 during SAMPLE A */
108 #define ADC_SCAN_OFF 0x0000 /* A/D Do notScan Input Selections for CH0+ during SAMPLE A */
109 #define ADC_SCAN_MASK (~ADC_SCAN_ON)
110 
111 #define ADC_CONVERT_CH0 0x0000 /* 10bit Only: A/D converts CH0 */
112 #define ADC_CONVERT_CH01 0x0100 /* 10bit Only: A/D converts CH0, CH1 */
113 #define ADC_CONVERT_CH0123 0x0300 /* 10bit Only: A/D converts CH0, CH1, CH2, CH3 */
114 
115 #define ADC_INTR_EACH_CONV 0x0000 /* Interrupts at the completion of conversion of each sample */
116 #define ADC_INTR_2_CONV 0x0004 /* Interrupts at the completion of conversion of 2 samples */
117 #define ADC_INTR_3_CONV 0x0008 /* Interrupts at the completion of conversion of 3 samples */
118 #define ADC_INTR_4_CONV 0x000C /* Interrupts at the completion of conversion of 4 samples */
119 #define ADC_INTR_5_CONV 0x0010 /* Interrupts at the completion of conversion of 5 samples */
120 #define ADC_INTR_6_CONV 0x0014 /* Interrupts at the completion of conversion of 6 samples */
121 #define ADC_INTR_7_CONV 0x0018 /* Interrupts at the completion of conversion of 7 samples */
122 #define ADC_INTR_8_CONV 0x001C /* Interrupts at the completion of conversion of 8 samples */
123 #define ADC_INTR_9_CONV 0x0020 /* Interrupts at the completion of conversion of 9 samples */
124 #define ADC_INTR_10_CONV 0x0024 /* Interrupts at the completion of conversion of 10 samples */
125 #define ADC_INTR_11_CONV 0x0028 /* Interrupts at the completion of conversion of 11 samples */
126 #define ADC_INTR_12_CONV 0x002C /* Interrupts at the completion of conversion of 12 samples */
127 #define ADC_INTR_13_CONV 0x0030 /* Interrupts at the completion of conversion of 13 samples */
128 #define ADC_INTR_14_CONV 0x0034 /* Interrupts at the completion of conversion of 14 samples */
129 #define ADC_INTR_15_CONV 0x0038 /* Interrupts at the completion of conversion of 15 samples */
130 #define ADC_INTR_16_CONV 0x003C /* Interrupts at the completion of conversion of 16 samples */
131 #define ADC_INTR_MASK (~ADC_INTR_16_CONV)
132 
133 /* BUFM bit defines */
134 #define ADC_ALT_BUF_ON 0x0002 /* Buffer configured as 2 8-word buffers */
135 #define ADC_ALT_BUF_OFF 0x0000 /* Buffer configured as 1 16-word buffer */
136 #define ADC_ALT_BUF_MASK (~ADC_ALT_BUF_ON)
137 /* BUFS bit define */
138 #define ADC_ALT_BUF_STATUS_2 0x0080 /* ADC is 2nd half of buffer, read from 1st half */
139 #define ADC_ALT_BUF_STATUS_MASK (~ADC_ALT_BUF_STATUS_MASK)
140 
141 /* A/D Uses channel input selects for SAMPLE A on first sample and SAMPLE B on next sample */
142 #define ADC_ALT_INPUT_ON 0x0001 /* alternate between MUXA and MUXB */
143 /* A/D Always uses channel input selects for SAMPLE A */
144 #define ADC_ALT_INPUT_OFF 0x0000 /* use MUXA only */
145 #define ADC_ALT_MASK (~ADC_ALT_INPUT_ON)
146 
147 /* defines for ADCON3 register */
148 #define ADC_CONV_CLK_INTERNAL_RC 0x8000 /* A/D internal RC clock */
149 #define ADC_CONV_CLK_SYSTEM 0x0000 /* Clock derived from system clock */
150 #define ADC_CONV_CLK_SOURCE_MASK (~ADC_CONV_CLK_INTERNAL_RC)
151 
152 #define ADC_SAMPLE_TIME_0 0x0000 /* A/D Auto Sample Time 0 Tad */
153 #define ADC_SAMPLE_TIME_1 0x0100 /* A/D Auto Sample Time 1 Tad */
154 #define ADC_SAMPLE_TIME_2 0x0200 /* A/D Auto Sample Time 2 Tad */
155 #define ADC_SAMPLE_TIME_3 0x0300 /* A/D Auto Sample Time 3 Tad */
156 #define ADC_SAMPLE_TIME_4 0x0400 /* A/D Auto Sample Time 4 Tad */
157 #define ADC_SAMPLE_TIME_5 0x0500 /* A/D Auto Sample Time 5 Tad */
158 #define ADC_SAMPLE_TIME_6 0x0600 /* A/D Auto Sample Time 6 Tad */
159 #define ADC_SAMPLE_TIME_7 0x0700 /* A/D Auto Sample Time 7 Tad */
160 #define ADC_SAMPLE_TIME_8 0x0800 /* A/D Auto Sample Time 8 Tad */
161 #define ADC_SAMPLE_TIME_9 0x0900 /* A/D Auto Sample Time 9 Tad */
162 #define ADC_SAMPLE_TIME_10 0x0A00 /* A/D Auto Sample Time 10 Tad */
163 #define ADC_SAMPLE_TIME_11 0x0B00 /* A/D Auto Sample Time 11 Tad */
164 #define ADC_SAMPLE_TIME_12 0x0C00 /* A/D Auto Sample Time 12 Tad */
165 #define ADC_SAMPLE_TIME_13 0x0D00 /* A/D Auto Sample Time 13 Tad */
166 #define ADC_SAMPLE_TIME_14 0x0E00 /* A/D Auto Sample Time 14 Tad */
167 #define ADC_SAMPLE_TIME_15 0x0F00 /* A/D Auto Sample Time 15 Tad */
168 #define ADC_SAMPLE_TIME_16 0x1000 /* A/D Auto Sample Time 16 Tad */
169 #define ADC_SAMPLE_TIME_17 0x1100 /* A/D Auto Sample Time 17 Tad */
170 #define ADC_SAMPLE_TIME_18 0x1200 /* A/D Auto Sample Time 18 Tad */
171 #define ADC_SAMPLE_TIME_19 0x1300 /* A/D Auto Sample Time 19 Tad */
172 #define ADC_SAMPLE_TIME_20 0x1400 /* A/D Auto Sample Time 20 Tad */
173 #define ADC_SAMPLE_TIME_21 0x1500 /* A/D Auto Sample Time 21 Tad */
174 #define ADC_SAMPLE_TIME_22 0x1600 /* A/D Auto Sample Time 22 Tad */
175 #define ADC_SAMPLE_TIME_23 0x1700 /* A/D Auto Sample Time 23 Tad */
176 #define ADC_SAMPLE_TIME_24 0x1800 /* A/D Auto Sample Time 24 Tad */
177 #define ADC_SAMPLE_TIME_25 0x1900 /* A/D Auto Sample Time 25 Tad */
178 #define ADC_SAMPLE_TIME_26 0x1A00 /* A/D Auto Sample Time 26 Tad */
179 #define ADC_SAMPLE_TIME_27 0x1B00 /* A/D Auto Sample Time 27 Tad */
180 #define ADC_SAMPLE_TIME_28 0x1C00 /* A/D Auto Sample Time 28 Tad */
181 #define ADC_SAMPLE_TIME_29 0x1D00 /* A/D Auto Sample Time 29 Tad */
182 #define ADC_SAMPLE_TIME_30 0x1E00 /* A/D Auto Sample Time 30 Tad */
183 #define ADC_SAMPLE_TIME_31 0x1F00 /* A/D Auto Sample Time 31 Tad */
184 #define ADC_SAMPLE_TIME_MASK (~ADC_SAMPLE_TIME_31)
185 
186 /* A/D conversion clock select bit ADCS<7:0>*/
187 #define ADC_CONV_CLK_256Tcy 0x00FF
188 #define ADC_CONV_CLK_255Tcy 0x00FE
189 #define ADC_CONV_CLK_254Tcy 0x00FD
190 #define ADC_CONV_CLK_253Tcy 0x00FC
191 #define ADC_CONV_CLK_252Tcy 0x00FB
192 #define ADC_CONV_CLK_251Tcy 0x00FA
193 #define ADC_CONV_CLK_250Tcy 0x00F9
194 #define ADC_CONV_CLK_249Tcy 0x00F8
195 #define ADC_CONV_CLK_248Tcy 0x00F7
196 #define ADC_CONV_CLK_247Tcy 0x00F6
197 #define ADC_CONV_CLK_246Tcy 0x00F5
198 #define ADC_CONV_CLK_245Tcy 0x00F4
199 #define ADC_CONV_CLK_244Tcy 0x00F3
200 #define ADC_CONV_CLK_243Tcy 0x00F2
201 #define ADC_CONV_CLK_242Tcy 0x00F1
202 #define ADC_CONV_CLK_241Tcy 0x00F0
203 #define ADC_CONV_CLK_240Tcy 0x00EF
204 #define ADC_CONV_CLK_239Tcy 0x00EE
205 #define ADC_CONV_CLK_238Tcy 0x00ED
206 #define ADC_CONV_CLK_237Tcy 0x00EC
207 #define ADC_CONV_CLK_236Tcy 0x00EB
208 #define ADC_CONV_CLK_235Tcy 0x00EA
209 #define ADC_CONV_CLK_234Tcy 0x00E9
210 #define ADC_CONV_CLK_233Tcy 0x00E8
211 #define ADC_CONV_CLK_232Tcy 0x00E7
212 #define ADC_CONV_CLK_231Tcy 0x00E6
213 #define ADC_CONV_CLK_230Tcy 0x00E5
214 #define ADC_CONV_CLK_229Tcy 0x00E4
215 #define ADC_CONV_CLK_228Tcy 0x00E3
216 #define ADC_CONV_CLK_227Tcy 0x00E2
217 #define ADC_CONV_CLK_226Tcy 0x00E1
218 #define ADC_CONV_CLK_225Tcy 0x00E0
219 #define ADC_CONV_CLK_224Tcy 0x00DF
220 #define ADC_CONV_CLK_223Tcy 0x00DE
221 #define ADC_CONV_CLK_222Tcy 0x00DD
222 #define ADC_CONV_CLK_221Tcy 0x00DC
223 #define ADC_CONV_CLK_220Tcy 0x00DB
224 #define ADC_CONV_CLK_219Tcy 0x00DA
225 #define ADC_CONV_CLK_218Tcy 0x00D9
226 #define ADC_CONV_CLK_217Tcy 0x00D8
227 #define ADC_CONV_CLK_216Tcy 0x00D7
228 #define ADC_CONV_CLK_215Tcy 0x00D6
229 #define ADC_CONV_CLK_214Tcy 0x00D5
230 #define ADC_CONV_CLK_213Tcy 0x00D4
231 #define ADC_CONV_CLK_212Tcy 0x00D3
232 #define ADC_CONV_CLK_211Tcy 0x00D2
233 #define ADC_CONV_CLK_210Tcy 0x00D1
234 #define ADC_CONV_CLK_209Tcy 0x00D0
235 #define ADC_CONV_CLK_208Tcy 0x00CF
236 #define ADC_CONV_CLK_207Tcy 0x00CE
237 #define ADC_CONV_CLK_206Tcy 0x00CD
238 #define ADC_CONV_CLK_205Tcy 0x00CC
239 #define ADC_CONV_CLK_204Tcy 0x00CB
240 #define ADC_CONV_CLK_203Tcy 0x00CA
241 #define ADC_CONV_CLK_202Tcy 0x00C9
242 #define ADC_CONV_CLK_201Tcy 0x00C8
243 #define ADC_CONV_CLK_200Tcy 0x00C7
244 #define ADC_CONV_CLK_199Tcy 0x00C6
245 #define ADC_CONV_CLK_198Tcy 0x00C5
246 #define ADC_CONV_CLK_197Tcy 0x00C4
247 #define ADC_CONV_CLK_196Tcy 0x00C3
248 #define ADC_CONV_CLK_195Tcy 0x00C2
249 #define ADC_CONV_CLK_194Tcy 0x00C1
250 #define ADC_CONV_CLK_193Tcy 0x00C0
251 #define ADC_CONV_CLK_192Tcy 0x00BF
252 #define ADC_CONV_CLK_191Tcy 0x00BE
253 #define ADC_CONV_CLK_190Tcy 0x00BD
254 #define ADC_CONV_CLK_189Tcy 0x00BC
255 #define ADC_CONV_CLK_188Tcy 0x00BB
256 #define ADC_CONV_CLK_187Tcy 0x00BA
257 #define ADC_CONV_CLK_186Tcy 0x00B9
258 #define ADC_CONV_CLK_185Tcy 0x00B8
259 #define ADC_CONV_CLK_184Tcy 0x00B7
260 #define ADC_CONV_CLK_183Tcy 0x00B6
261 #define ADC_CONV_CLK_182Tcy 0x00B5
262 #define ADC_CONV_CLK_181Tcy 0x00B4
263 #define ADC_CONV_CLK_180Tcy 0x00B3
264 #define ADC_CONV_CLK_179Tcy 0x00B2
265 #define ADC_CONV_CLK_178Tcy 0x00B1
266 #define ADC_CONV_CLK_177Tcy 0x00B0
267 #define ADC_CONV_CLK_176Tcy 0x00AF
268 #define ADC_CONV_CLK_175Tcy 0x00AE
269 #define ADC_CONV_CLK_174Tcy 0x00AD
270 #define ADC_CONV_CLK_173Tcy 0x00AC
271 #define ADC_CONV_CLK_172Tcy 0x00AB
272 #define ADC_CONV_CLK_171Tcy 0x00AA
273 #define ADC_CONV_CLK_170Tcy 0x00A9
274 #define ADC_CONV_CLK_169Tcy 0x00A8
275 #define ADC_CONV_CLK_168Tcy 0x00A7
276 #define ADC_CONV_CLK_167Tcy 0x00A6
277 #define ADC_CONV_CLK_166Tcy 0x00A5
278 #define ADC_CONV_CLK_165Tcy 0x00A4
279 #define ADC_CONV_CLK_164Tcy 0x00A3
280 #define ADC_CONV_CLK_163Tcy 0x00A2
281 #define ADC_CONV_CLK_162Tcy 0x00A1
282 #define ADC_CONV_CLK_161Tcy 0x00A0
283 #define ADC_CONV_CLK_160Tcy 0x009F
284 #define ADC_CONV_CLK_159Tcy 0x009E
285 #define ADC_CONV_CLK_158Tcy 0x009D
286 #define ADC_CONV_CLK_157Tcy 0x009C
287 #define ADC_CONV_CLK_156Tcy 0x009B
288 #define ADC_CONV_CLK_155Tcy 0x009A
289 #define ADC_CONV_CLK_154Tcy 0x0099
290 #define ADC_CONV_CLK_153Tcy 0x0098
291 #define ADC_CONV_CLK_152Tcy 0x0097
292 #define ADC_CONV_CLK_151Tcy 0x0096
293 #define ADC_CONV_CLK_150Tcy 0x0095
294 #define ADC_CONV_CLK_149Tcy 0x0094
295 #define ADC_CONV_CLK_148Tcy 0x0093
296 #define ADC_CONV_CLK_147Tcy 0x0092
297 #define ADC_CONV_CLK_146Tcy 0x0091
298 #define ADC_CONV_CLK_145Tcy 0x0090
299 #define ADC_CONV_CLK_144Tcy 0x008F
300 #define ADC_CONV_CLK_143Tcy 0x008E
301 #define ADC_CONV_CLK_142Tcy 0x008D
302 #define ADC_CONV_CLK_141Tcy 0x008C
303 #define ADC_CONV_CLK_140Tcy 0x008B
304 #define ADC_CONV_CLK_139Tcy 0x008A
305 #define ADC_CONV_CLK_138Tcy 0x0089
306 #define ADC_CONV_CLK_137Tcy 0x0088
307 #define ADC_CONV_CLK_136Tcy 0x0087
308 #define ADC_CONV_CLK_135Tcy 0x0086
309 #define ADC_CONV_CLK_134Tcy 0x0085
310 #define ADC_CONV_CLK_133Tcy 0x0084
311 #define ADC_CONV_CLK_132Tcy 0x0083
312 #define ADC_CONV_CLK_131Tcy 0x0082
313 #define ADC_CONV_CLK_130Tcy 0x0081
314 #define ADC_CONV_CLK_129Tcy 0x0080
315 #define ADC_CONV_CLK_128Tcy 0x007F
316 #define ADC_CONV_CLK_127Tcy 0x007E
317 #define ADC_CONV_CLK_126Tcy 0x007D
318 #define ADC_CONV_CLK_125Tcy 0x007C
319 #define ADC_CONV_CLK_124Tcy 0x007B
320 #define ADC_CONV_CLK_123Tcy 0x007A
321 #define ADC_CONV_CLK_122Tcy 0x0079
322 #define ADC_CONV_CLK_121Tcy 0x0078
323 #define ADC_CONV_CLK_120Tcy 0x0077
324 #define ADC_CONV_CLK_119Tcy 0x0076
325 #define ADC_CONV_CLK_118Tcy 0x0075
326 #define ADC_CONV_CLK_117Tcy 0x0074
327 #define ADC_CONV_CLK_116Tcy 0x0073
328 #define ADC_CONV_CLK_115Tcy 0x0072
329 #define ADC_CONV_CLK_114Tcy 0x0071
330 #define ADC_CONV_CLK_113Tcy 0x0070
331 #define ADC_CONV_CLK_112Tcy 0x006F
332 #define ADC_CONV_CLK_111Tcy 0x006E
333 #define ADC_CONV_CLK_110Tcy 0x006D
334 #define ADC_CONV_CLK_109Tcy 0x006C
335 #define ADC_CONV_CLK_108Tcy 0x006B
336 #define ADC_CONV_CLK_107Tcy 0x006A
337 #define ADC_CONV_CLK_106Tcy 0x0069
338 #define ADC_CONV_CLK_105Tcy 0x0068
339 #define ADC_CONV_CLK_104Tcy 0x0067
340 #define ADC_CONV_CLK_103Tcy 0x0066
341 #define ADC_CONV_CLK_102Tcy 0x0065
342 #define ADC_CONV_CLK_101Tcy 0x0064
343 #define ADC_CONV_CLK_100Tcy 0x0063
344 #define ADC_CONV_CLK_99Tcy 0x0062
345 #define ADC_CONV_CLK_98Tcy 0x0061
346 #define ADC_CONV_CLK_97Tcy 0x0060
347 #define ADC_CONV_CLK_96Tcy 0x005F
348 #define ADC_CONV_CLK_95Tcy 0x005E
349 #define ADC_CONV_CLK_94Tcy 0x005D
350 #define ADC_CONV_CLK_93Tcy 0x005C
351 #define ADC_CONV_CLK_92Tcy 0x005B
352 #define ADC_CONV_CLK_91Tcy 0x005A
353 #define ADC_CONV_CLK_90Tcy 0x0059
354 #define ADC_CONV_CLK_89Tcy 0x0058
355 #define ADC_CONV_CLK_88Tcy 0x0057
356 #define ADC_CONV_CLK_87Tcy 0x0056
357 #define ADC_CONV_CLK_86Tcy 0x0055
358 #define ADC_CONV_CLK_85Tcy 0x0054
359 #define ADC_CONV_CLK_84Tcy 0x0053
360 #define ADC_CONV_CLK_83Tcy 0x0052
361 #define ADC_CONV_CLK_82Tcy 0x0051
362 #define ADC_CONV_CLK_81Tcy 0x0050
363 #define ADC_CONV_CLK_80Tcy 0x004F
364 #define ADC_CONV_CLK_79Tcy 0x004E
365 #define ADC_CONV_CLK_78Tcy 0x004D
366 #define ADC_CONV_CLK_77Tcy 0x004C
367 #define ADC_CONV_CLK_76Tcy 0x004B
368 #define ADC_CONV_CLK_75Tcy 0x004A
369 #define ADC_CONV_CLK_74Tcy 0x0049
370 #define ADC_CONV_CLK_73Tcy 0x0048
371 #define ADC_CONV_CLK_72Tcy 0x0047
372 #define ADC_CONV_CLK_71Tcy 0x0046
373 #define ADC_CONV_CLK_70Tcy 0x0045
374 #define ADC_CONV_CLK_69Tcy 0x0044
375 #define ADC_CONV_CLK_68Tcy 0x0043
376 #define ADC_CONV_CLK_67Tcy 0x0042
377 #define ADC_CONV_CLK_66Tcy 0x0041
378 #define ADC_CONV_CLK_65Tcy 0x0040
379 #define ADC_CONV_CLK_64Tcy 0x003F
380 #define ADC_CONV_CLK_63Tcy 0x003E
381 #define ADC_CONV_CLK_62Tcy 0x003D
382 #define ADC_CONV_CLK_61Tcy 0x003C
383 #define ADC_CONV_CLK_60Tcy 0x003B
384 #define ADC_CONV_CLK_59Tcy 0x003A
385 #define ADC_CONV_CLK_58Tcy 0x0039
386 #define ADC_CONV_CLK_57Tcy 0x0038
387 #define ADC_CONV_CLK_56Tcy 0x0037
388 #define ADC_CONV_CLK_55Tcy 0x0036
389 #define ADC_CONV_CLK_54Tcy 0x0035
390 #define ADC_CONV_CLK_53Tcy 0x0034
391 #define ADC_CONV_CLK_52Tcy 0x0033
392 #define ADC_CONV_CLK_51Tcy 0x0032
393 #define ADC_CONV_CLK_50Tcy 0x0031
394 #define ADC_CONV_CLK_49Tcy 0x0030
395 #define ADC_CONV_CLK_48Tcy 0x002F
396 #define ADC_CONV_CLK_47Tcy 0x002E
397 #define ADC_CONV_CLK_46Tcy 0x002D
398 #define ADC_CONV_CLK_45Tcy 0x002C
399 #define ADC_CONV_CLK_44Tcy 0x002B
400 #define ADC_CONV_CLK_43Tcy 0x002A
401 #define ADC_CONV_CLK_42Tcy 0x0029
402 #define ADC_CONV_CLK_41Tcy 0x0028
403 #define ADC_CONV_CLK_40Tcy 0x0027
404 #define ADC_CONV_CLK_39Tcy 0x0026
405 #define ADC_CONV_CLK_38Tcy 0x0025
406 #define ADC_CONV_CLK_37Tcy 0x0024
407 #define ADC_CONV_CLK_36Tcy 0x0023
408 #define ADC_CONV_CLK_35Tcy 0x0022
409 #define ADC_CONV_CLK_34Tcy 0x0021
410 #define ADC_CONV_CLK_33Tcy 0x0020
411 #define ADC_CONV_CLK_32Tcy 0x001F
412 #define ADC_CONV_CLK_31Tcy 0x001E
413 #define ADC_CONV_CLK_30Tcy 0x001D
414 #define ADC_CONV_CLK_29Tcy 0x001C
415 #define ADC_CONV_CLK_28Tcy 0x001B
416 #define ADC_CONV_CLK_27Tcy 0x001A
417 #define ADC_CONV_CLK_26Tcy 0x0019
418 #define ADC_CONV_CLK_25Tcy 0x0018
419 #define ADC_CONV_CLK_24Tcy 0x0017
420 #define ADC_CONV_CLK_23Tcy 0x0016
421 #define ADC_CONV_CLK_22Tcy 0x0015
422 #define ADC_CONV_CLK_21Tcy 0x0014
423 #define ADC_CONV_CLK_20Tcy 0x0013
424 #define ADC_CONV_CLK_19Tcy 0x0012
425 #define ADC_CONV_CLK_18Tcy 0x0011
426 #define ADC_CONV_CLK_17Tcy 0x0010
427 #define ADC_CONV_CLK_16Tcy 0x000F
428 #define ADC_CONV_CLK_15Tcy 0x000E
429 #define ADC_CONV_CLK_14Tcy 0x000D
430 #define ADC_CONV_CLK_13Tcy 0x000C
431 #define ADC_CONV_CLK_12Tcy 0x000B
432 #define ADC_CONV_CLK_11Tcy 0x000A
433 #define ADC_CONV_CLK_10Tcy 0x0009
434 #define ADC_CONV_CLK_9Tcy 0x0008
435 #define ADC_CONV_CLK_8Tcy 0x0007
436 #define ADC_CONV_CLK_7Tcy 0x0006
437 #define ADC_CONV_CLK_6Tcy 0x0005
438 #define ADC_CONV_CLK_5Tcy 0x0004
439 #define ADC_CONV_CLK_4Tcy 0x0003
440 #define ADC_CONV_CLK_3Tcy 0x0002
441 #define ADC_CONV_CLK_2Tcy 0x0001
442 #define ADC_CONV_CLK_1Tcy 0x0000
443 #define ADC_CONV_CLK_MASK (~ADC_CONV_CLK_256Tcy)
444 
445 /* ADxCON4 register */
446 #define ADC_DMA_BUF_LOC_128 0x0007 /* Allocates words of buffer to each analog input */
447 #define ADC_DMA_BUF_LOC_64 0x0006 /* Allocates words of buffer to each analog input */
448 #define ADC_DMA_BUF_LOC_32 0x0005 /* Allocates words of buffer to each analog input */
449 #define ADC_DMA_BUF_LOC_16 0x0004 /* Allocates words of buffer to each analog input */
450 #define ADC_DMA_BUF_LOC_8 0x0003 /* Allocates words of buffer to each analog input */
451 #define ADC_DMA_BUF_LOC_4 0x0002 /* Allocates words of buffer to each analog input */
452 #define ADC_DMA_BUF_LOC_2 0x0001 /* Allocates words of buffer to each analog input */
453 #define ADC_DMA_BUF_LOC_1 0x0000 /* Allocates words of buffer to each analog input */
454 #define ADC_DMA_BUF_LOC_MASK (~ADC_DMA_BUF_LOC_128)
455 
456 /* ADC1 Input channel 0 select register (AD1CHS0 regsiter) */
457 #define ADC_CH0_NEG_SAMPLEB_AN1 0x8000 /* CH0 negative input is AN1 */
458 #define ADC_CH0_NEG_SAMPLEB_VREFN 0x0000 /* CH0 negative input is VREF- */
459 #define ADC_CH0_NEG_SAMPLEB_MASK (~ADC_CH0_NEG_SAMPLEB_AN1)
460 
461 #define ADC_CH0_POS_SAMPLEB_AN15 0x0F00 /* A/D CH0 pos i/p sel for SAMPLE B is AN15 */
462 #define ADC_CH0_POS_SAMPLEB_AN14 0x0E00 /* A/D CH0 pos i/p sel for SAMPLE B is AN14 */
463 #define ADC_CH0_POS_SAMPLEB_AN13 0x0D00 /* A/D CH0 pos i/p sel for SAMPLE B is AN13 */
464 #define ADC_CH0_POS_SAMPLEB_AN12 0x0C00 /* A/D CH0 pos i/p sel for SAMPLE B is AN12 */
465 #define ADC_CH0_POS_SAMPLEB_AN11 0x0B00 /* A/D CH0 pos i/p sel for SAMPLE B is AN11 */
466 #define ADC_CH0_POS_SAMPLEB_AN10 0x0A00 /* A/D CH0 pos i/p sel for SAMPLE B is AN10 */
467 #define ADC_CH0_POS_SAMPLEB_AN9 0x0900 /* A/D CH0 pos i/p sel for SAMPLE B is AN9 */
468 #define ADC_CH0_POS_SAMPLEB_AN8 0x0800 /* A/D CH0 pos i/p sel for SAMPLE B is AN8 */
469 #define ADC_CH0_POS_SAMPLEB_AN7 0x0700 /* A/D CH0 pos i/p sel for SAMPLE B is AN7 */
470 #define ADC_CH0_POS_SAMPLEB_AN6 0x0600 /* A/D CH0 pos i/p sel for SAMPLE B is AN6 */
471 #define ADC_CH0_POS_SAMPLEB_AN5 0x0500 /* A/D CH0 pos i/p sel for SAMPLE B is AN5 */
472 #define ADC_CH0_POS_SAMPLEB_AN4 0x0400 /* A/D CH0 pos i/p sel for SAMPLE B is AN4 */
473 #define ADC_CH0_POS_SAMPLEB_AN3 0x0300 /* A/D CH0 pos i/p sel for SAMPLE B is AN3 */
474 #define ADC_CH0_POS_SAMPLEB_AN2 0x0200 /* A/D CH0 pos i/p sel for SAMPLE B is AN2 */
475 #define ADC_CH0_POS_SAMPLEB_AN1 0x0100 /* A/D CH0 pos i/p sel for SAMPLE B is AN1 */
476 #define ADC_CH0_POS_SAMPLEB_AN0 0x0000 /* A/D CH0 pos i/p sel for SAMPLE B is AN0 */
477 #define ADC_CH0_POS_SAMPLEB_MASK (~ADC_CH0_POS_SAMPLEB_AN15)
478 
479 #define ADC_CH0_NEG_SAMPLEA_AN1 0x0080 /*A/D CH0 neg I/P sel for SAMPLE A is AN1 */
480 #define ADC_CH0_NEG_SAMPLEA_VREFN 0x0000 /*A/D CH0 neg I/P sel for SAMPLE A is Vrefn */
481 #define ADC_CH0_NEG_SAMPLEA_MASK (~ADC_CH0_NEG_SAMPLEA_AN1)
482 
483 #define ADC_CH0_POS_SAMPLEA_AN15 0x000F /* A/D Chan 0 pos i/p sel for SAMPLE A is AN15 */
484 #define ADC_CH0_POS_SAMPLEA_AN14 0x000E /* A/D Chan 0 pos i/p sel for SAMPLE A is AN14 */
485 #define ADC_CH0_POS_SAMPLEA_AN13 0x000D /* A/D Chan 0 pos i/p sel for SAMPLE A is AN13 */
486 #define ADC_CH0_POS_SAMPLEA_AN12 0x000C /* A/D Chan 0 pos i/p sel for SAMPLE A is AN12 */
487 #define ADC_CH0_POS_SAMPLEA_AN11 0x000B /* A/D Chan 0 pos i/p sel for SAMPLE A is AN11 */
488 #define ADC_CH0_POS_SAMPLEA_AN10 0x000A /* A/D Chan 0 pos i/p sel for SAMPLE A is AN10 */
489 #define ADC_CH0_POS_SAMPLEA_AN9 0x0009 /* A/D Chan 0 pos i/p sel for SAMPLE A is AN9 */
490 #define ADC_CH0_POS_SAMPLEA_AN8 0x0008 /* A/D Chan 0 pos i/p sel for SAMPLE A is AN8 */
491 #define ADC_CH0_POS_SAMPLEA_AN7 0x0007 /* A/D Chan 0 pos i/p sel for SAMPLE A is AN7 */
492 #define ADC_CH0_POS_SAMPLEA_AN6 0x0006 /* A/D Chan 0 pos i/p sel for SAMPLE A is AN6 */
493 #define ADC_CH0_POS_SAMPLEA_AN5 0x0005 /* A/D Chan 0 pos i/p sel for SAMPLE A is AN5 */
494 #define ADC_CH0_POS_SAMPLEA_AN4 0x0004 /* A/D Chan 0 pos i/p sel for SAMPLE A is AN4 */
495 #define ADC_CH0_POS_SAMPLEA_AN3 0x0003 /* A/D Chan 0 pos i/p sel for SAMPLE A is AN3 */
496 #define ADC_CH0_POS_SAMPLEA_AN2 0x0002 /* A/D Chan 0 pos i/p sel for SAMPLE A is AN2 */
497 #define ADC_CH0_POS_SAMPLEA_AN1 0x0001 /* A/D Chan 0 pos i/p sel for SAMPLE A is AN1 */
498 #define ADC_CH0_POS_SAMPLEA_AN0 0x0000 /* A/D Chan 0 pos i/p sel for SAMPLE A is AN0 */
499 #define ADC_CH0_POS_SAMPLEA_MASK (~ADC_CH0_POS_SAMPLEA_AN15)
500 
501 /* ADC1 Input channel 1,2,3 select register (AD1CHS123 register) */
502 #define ADC_CH123_NEG_SAMPLEB_AN9AN10AN11 0x0600 /* SAMPLE B neg.input for CHs 1,2,3 is AN9,AN10,AN11 */
503 #define ADC_CH123_NEG_SAMPLEB_AN6AN7AN8 0x0400 /* SAMPLE B neg.input for CHs 1,2,3 is AN6,AN7,AN8 */
504 #define ADC_CH123_NEG_SAMPLEB_VREFN 0x0000 /* SAMPLE B neg.input for CHs 1,2,3 is VREF- */
505 #define ADC_CH123_NEG_SAMPLEB_MASK (~ADC_CH123_NEG_SAMPLEB_AN9_AN10_AN11)
506 
507 #define ADC_CH123_POS_SAMPLEB_AN3AN4AN5 0x0100 /* SAMPLE B pos.input for CHs 1,2,3 is AN3,AN4,AN5 */
508 #define ADC_CH123_POS_SAMPLEB_AN0AN1AN2 0x0000 /* SAMPLE B pos.input for CHs 1,2,3 is AN3,AN4,AN5 */
509 #define ADC_CH123_POS_SAMPLEB_MASK (~ADC_CH123_POS_SAMPLEB_AN3_AN4_AN5)
510 
511 #define ADC_CH123_NEG_SAMPLEA_AN9AN10AN11 0x0006 /* SAMPLE A neg.input for CHs 1,2,3 is AN9,AN10,AN11 */
512 #define ADC_CH123_NEG_SAMPLEA_AN6AN7AN8 0x0004 /* SAMPLE A neg.input for CHs 1,2,3 is AN6,AN7,AN8 */
513 #define ADC_CH123_NEG_SAMPLEA_VREFN 0x0000 /* SAMPLE A neg.input for CHs 1,2,3 is VREF- */
514 #define ADC_CH123_NEG_SAMPLEA_MASK (~ADC_CH123_NEG_SAMPLEA_AN9_AN10_AN11)
515 
516 #define ADC_CH123_POS_SAMPLEA_AN3AN4AN5 0x0001 /* SAMPLE A pos.input for CHs 1,2,3 is AN3,AN4,AN5 */
517 #define ADC_CH123_POS_SAMPLEA_AN0AN1AN2 0x0000 /* SAMPLE A pos.input for CHs 1,2,3 is AN3,AN4,AN5 */
518 #define ADC_CH123_POS_SAMPLEA_MASK (~ADC_CH123_POS_SAMPLEA_AN3_AN4_AN5)
519 
520 
521 /*defines for ADxPCFGL register */
522 #define ENABLE_AN0_ANA 0x0001 /*Enable AN0 in analog mode */
523 #define ENABLE_AN1_ANA 0x0002 /*Enable AN1 in analog mode */
524 #define ENABLE_AN2_ANA 0x0004 /*Enable AN2 in analog mode */
525 #define ENABLE_AN3_ANA 0x0008 /*Enable AN3 in analog mode */
526 #define ENABLE_AN4_ANA 0x0010 /*Enable AN4 in analog mode */
527 #define ENABLE_AN5_ANA 0x0020 /*Enable AN5 in analog mode */
528 #define ENABLE_AN6_ANA 0x0040 /*Enable AN6 in analog mode */
529 #define ENABLE_AN7_ANA 0x0080 /*Enable AN7 in analog mode */
530 #define ENABLE_AN8_ANA 0x0100 /*Enable AN8 in analog mode */
531 #define ENABLE_AN9_ANA 0x0200 /*Enable AN9 in analog mode */
532 #define ENABLE_AN10_ANA 0x0400 /*Enable AN10 in analog mode */
533 #define ENABLE_AN11_ANA 0x0800 /*Enable AN11 in analog mode */
534 #define ENABLE_AN12_ANA 0x1000 /*Enable AN12 in analog mode */
535 #define ENABLE_AN13_ANA 0x2000 /*Enable AN13 in analog mode */
536 #define ENABLE_AN14_ANA 0x4000 /*Enable AN14 in analog mode */
537 #define ENABLE_AN15_ANA 0x8000 /*Enable AN15 in analog mode */
538 
539 #define ENABLE_ALL_ANA_0_15 0xFFFF /*Enable AN0-AN15 in analog mode */
540 #define ENABLE_ALL_DIG_0_15 0x0000 /*Enable AN0-AN15 in Digital mode */
541 
542 /*defines for ADxCSSL register */
543 #define ADC_SCAN_AN0 0x0001 /*Enable Input Scan AN0 */
544 #define ADC_SCAN_AN1 0x0002 /*Enable Input Scan AN1 */
545 #define ADC_SCAN_AN2 0x0004 /*Enable Input Scan AN2 */
546 #define ADC_SCAN_AN3 0x0008 /*Enable Input Scan AN3 */
547 #define ADC_SCAN_AN4 0x0010 /*Enable Input Scan AN4 */
548 #define ADC_SCAN_AN5 0x0020 /*Enable Input Scan AN5 */
549 #define ADC_SCAN_AN6 0x0040 /*Enable Input Scan AN6 */
550 #define ADC_SCAN_AN7 0x0080 /*Enable Input Scan AN7 */
551 #define ADC_SCAN_AN8 0x0100 /*Enable Input Scan AN8 */
552 #define ADC_SCAN_AN9 0x0200 /*Enable Input Scan AN9 */
553 #define ADC_SCAN_AN10 0x0400 /*Enable Input Scan AN10 */
554 #define ADC_SCAN_AN11 0x0800 /*Enable Input Scan AN11 */
555 #define ADC_SCAN_AN12 0x1000 /*Enable Input Scan AN12 */
556 #define ADC_SCAN_AN13 0x2000 /*Enable Input Scan AN13 */
557 #define ADC_SCAN_AN14 0x4000 /*Enable Input Scan AN14 */
558 #define ADC_SCAN_AN15 0x8000 /*Enable Input Scan AN15 */
559 
560 #define ENABLE_ALL_INPUT_SCAN 0xFFFF /*Enable Input Scan AN0-AN15 */
561 #define DISABLE_ALL_INPU_SCAN 0x0000 /*Disable Input Scan AN0-AN15 */
562 
563 /*defines for ADxCSSH register */
564 #define ADC_SCAN_AN16 0x0001 /*Enable Input Scan AN16 */
565 #define ADC_SCAN_AN17 0x0002 /*Enable Input Scan AN17 */
566 #define ADC_SCAN_AN18 0x0004 /*Enable Input Scan AN18 */
567 #define ADC_SCAN_AN19 0x0008 /*Enable Input Scan AN19 */
568 #define ADC_SCAN_AN20 0x0010 /*Enable Input Scan AN20 */
569 #define ADC_SCAN_AN21 0x0020 /*Enable Input Scan AN21 */
570 #define ADC_SCAN_AN22 0x0040 /*Enable Input Scan AN22 */
571 #define ADC_SCAN_AN23 0x0080 /*Enable Input Scan AN23 */
572 #define ADC_SCAN_AN24 0x0100 /*Enable Input Scan AN24 */
573 #define ADC_SCAN_AN25 0x0200 /*Enable Input Scan AN25 */
574 #define ADC_SCAN_AN26 0x0400 /*Enable Input Scan AN26 */
575 #define ADC_SCAN_AN27 0x0800 /*Enable Input Scan AN27 */
576 #define ADC_SCAN_AN28 0x1000 /*Enable Input Scan AN28 */
577 #define ADC_SCAN_AN29 0x2000 /*Enable Input Scan AN29 */
578 #define ADC_SCAN_AN30 0x4000 /*Enable Input Scan AN30 */
579 #define ADC_SCAN_AN31 0x8000 /*Enable Input Scan AN31 */
580 
581 /* Setting the priority of adc interrupt */
582 #define ADC_INT_PRI_0 0x0000
583 #define ADC_INT_PRI_1 0x0001
584 #define ADC_INT_PRI_2 0x0002
585 #define ADC_INT_PRI_3 0x0003
586 #define ADC_INT_PRI_4 0x0004
587 #define ADC_INT_PRI_5 0x0005
588 #define ADC_INT_PRI_6 0x0006
589 #define ADC_INT_PRI_7 0x0007
590 
591 /* enable / disable interrupts */
592 
593 #define ADC_INT_ENABLE 0x0008
594 #define ADC_INT_DISABLE ~ADC_INT_ENABLE
595 
596 /* ADxCON4 */
597 #define ADC_1_WORD_PER_INPUT 0
598 #define ADC_2_WORD_PER_INPUT 1
599 #define ADC_4_WORD_PER_INPUT 2
600 #define ADC_8_WORD_PER_INPUT 3
601 #define ADC_16_WORD_PER_INPUT 4
602 #define ADC_32_WORD_PER_INPUT 5
603 #define ADC_64_WORD_PER_INPUT 6
604 #define ADC_128_WORD_PER_INPUT 7
605 
606 
607 
608 
609 #endif // _PIC24_ADC_H_