40 #if (NUM_UART_MODS >= 1)
86 #ifdef UART1_TX_INTERRUPT
90 #ifndef UART1_TX_FIFO_SIZE
91 #define UART1_TX_FIFO_SIZE 32 //choose a size
94 #ifndef UART1_TX_INTERRUPT_PRIORITY
95 #define UART1_TX_INTERRUPT_PRIORITY 1
98 volatile uint8_t au8_txFifo1[UART1_TX_FIFO_SIZE];
99 volatile uint16_t u16_txFifo1Head = 0;
100 volatile uint16_t u16_txFifo1Tail = 0;
109 u16_tmp = u16_txFifo1Head;
111 if (u16_tmp == UART1_TX_FIFO_SIZE) u16_tmp = 0;
112 while (u16_tmp == u16_txFifo1Tail)
115 au8_txFifo1[u16_tmp] = u8_c;
116 u16_txFifo1Head = u16_tmp;
120 void _ISR _U1TXInterrupt (
void) {
121 if (u16_txFifo1Head == u16_txFifo1Tail) {
127 if (u16_txFifo1Tail == UART1_TX_FIFO_SIZE)
131 U1TXREG = au8_txFifo1[u16_txFifo1Tail];
149 #ifdef UART1_RX_INTERRUPT
151 #ifndef UART1_RX_FIFO_SIZE
152 #define UART1_RX_FIFO_SIZE 32 //choose a size
155 #ifndef UART1_RX_INTERRUPT_PRIORITY
156 #define UART1_RX_INTERRUPT_PRIORITY 1
159 volatile uint8_t au8_rxFifo1[UART1_RX_FIFO_SIZE];
160 volatile uint16_t u16_rxFifo1Head = 0;
161 volatile uint16_t u16_rxFifo1Tail = 0;
167 return(u16_rxFifo1Head != u16_rxFifo1Tail);
175 while (u16_rxFifo1Head == u16_rxFifo1Tail)
178 if (u16_rxFifo1Tail == UART1_RX_FIFO_SIZE) u16_rxFifo1Tail=0;
179 return au8_rxFifo1[u16_rxFifo1Tail];
182 void _ISR _U1RXInterrupt (
void) {
189 if (u16_rxFifo1Head == UART1_RX_FIFO_SIZE)
191 if (u16_rxFifo1Head == u16_rxFifo1Tail) {
195 au8_rxFifo1[u16_rxFifo1Head] = u8_c;
226 #ifndef DEFAULT_BRGH1
227 #define DEFAULT_BRGH1 DEFAULT_BRGH
230 #if (DEFAULT_BRGH1 != 0) && (DEFAULT_BRGH1 != 1)
231 #error Invalid value specified for DEFAULT_BRGH1
255 #if (HARDWARE_PLATFORM == EXPLORER16_100P)
261 #if (HARDWARE_PLATFORM == DANGEROUS_WEB)
262 CONFIG_RP14_AS_DIG_PIN();
264 CONFIG_RP15_AS_DIG_PIN();
266 CONFIG_RP10_AS_DIG_PIN();
270 DISABLE_U1TX_ANALOG();
271 DISABLE_U1RX_ANALOG();
272 #elif (HARDWARE_PLATFORM == STARTER_BOARD_28P)
273 CONFIG_RP9_AS_DIG_PIN();
275 CONFIG_RP8_AS_DIG_PIN();
280 DISABLE_U1TX_ANALOG();
281 DISABLE_U1RX_ANALOG();
282 #elif (HARDWARE_PLATFORM == DEFAULT_DESIGN)
283 #if ( defined(__PIC24E__) || defined(__dsPIC33E__))
285 CONFIG_RP43_AS_DIG_PIN();
289 CONFIG_RP11_AS_DIG_PIN();
295 DISABLE_U1TX_ANALOG();
296 DISABLE_U1RX_ANALOG();
298 #error Unknown hardware platform.
301 #warning UART1 pin mappings not defined. See comments below for more info.
325 u32_brg =
FCY/u32_baudRate;
326 #if (DEFAULT_BRGH1 == 0)
327 if ((u32_brg & 0x0FL) >= 8) u32_brg = u32_brg/16;
328 else u32_brg = u32_brg/16 - 1;
330 if ((brg & 0x03L) >= 2) u32_brg = u32_brg/4;
331 else u32_brg = u32_brg/4 - 1;
336 #if (DEFAULT_BRGH1 == 0)
337 f_brg = (((float)
FCY)/((float) u32_baudRate)/16.0) - 1.0;
339 f_brg = (((float)
FCY)/((float) u32_baudRate)/4.0) - 1.0;
388 ASSERT(u32_baudRate >= 1000L);
397 while (U1STAbits.PERR || U1STAbits.FERR) {
402 #ifdef UART1_RX_INTERRUPT
404 _U1RXIP = UART1_RX_INTERRUPT_PRIORITY;
407 #ifdef UART1_TX_INTERRUPT
409 _U1TXIP = UART1_TX_INTERRUPT_PRIORITY;
415 #endif // #if (NUM_UARTS >= 1)
459 #if (NUM_UART_MODS >= 2)
485 void checkRxErrorUART2(
void) {
488 if (U2STAbits.PERR) {
492 if (U2STAbits.FERR) {
496 if (U2STAbits.OERR) {
505 #ifdef UART2_TX_INTERRUPT
509 #ifndef UART2_TX_FIFO_SIZE
510 #define UART2_TX_FIFO_SIZE 32 //choose a size
513 #ifndef UART2_TX_INTERRUPT_PRIORITY
514 #define UART2_TX_INTERRUPT_PRIORITY 1
517 volatile uint8_t au8_txFifo2[UART2_TX_FIFO_SIZE];
518 volatile uint16_t u16_txFifo2Head = 0;
519 volatile uint16_t u16_txFifo2Tail = 0;
528 u16_tmp = u16_txFifo2Head;
530 if (u16_tmp == UART2_TX_FIFO_SIZE) u16_tmp = 0;
531 while (u16_tmp == u16_txFifo2Tail)
534 au8_txFifo2[u16_tmp] = u8_c;
535 u16_txFifo2Head = u16_tmp;
539 void _ISR _U2TXInterrupt (
void) {
540 if (u16_txFifo2Head == u16_txFifo2Tail) {
546 if (u16_txFifo2Tail == UART2_TX_FIFO_SIZE)
550 U2TXREG = au8_txFifo2[u16_txFifo2Tail];
562 while (IS_TRANSMIT_BUFFER_FULL_UART2())
568 #ifdef UART2_RX_INTERRUPT
570 #ifndef UART2_RX_FIFO_SIZE
571 #define UART2_RX_FIFO_SIZE 32 //choose a size
574 #ifndef UART2_RX_INTERRUPT_PRIORITY
575 #define UART2_RX_INTERRUPT_PRIORITY 1
578 volatile uint8_t au8_rxFifo2[UART2_RX_FIFO_SIZE];
579 volatile uint16_t u16_rxFifo2Head = 0;
580 volatile uint16_t u16_rxFifo2Tail = 0;
586 return(u16_rxFifo2Head != u16_rxFifo2Tail);
594 while (u16_rxFifo2Head == u16_rxFifo2Tail)
597 if (u16_rxFifo2Tail == UART2_RX_FIFO_SIZE) u16_rxFifo2Tail=0;
598 return au8_rxFifo2[u16_rxFifo2Tail];
601 void _ISR _U2RXInterrupt (
void) {
608 if (u16_rxFifo2Head == UART2_RX_FIFO_SIZE)
610 if (u16_rxFifo2Head == u16_rxFifo2Tail) {
614 au8_rxFifo2[u16_rxFifo2Head] = u8_c;
622 return(IS_CHAR_READY_UART2());
633 while (!IS_CHAR_READY_UART2())
645 #ifndef DEFAULT_BRGH2
646 #define DEFAULT_BRGH2 DEFAULT_BRGH
649 #if (DEFAULT_BRGH2 != 0) && (DEFAULT_BRGH2 != 1)
650 #error Invalid value specified for DEFAULT_BRGH2
662 void configUART2(
uint32_t u32_baudRate) {
674 #if (HARDWARE_PLATFORM == EXPLORER16_100P)
680 #if (HARDWARE_PLATFORM == DANGEROUS_WEB)
681 CONFIG_RP14_AS_DIG_PIN();
683 CONFIG_RP15_AS_DIG_PIN();
685 CONFIG_RP10_AS_DIG_PIN();
689 DISABLE_U1TX_ANALOG();
690 DISABLE_U1RX_ANALOG();
691 #elif (HARDWARE_PLATFORM == STARTER_BOARD_28P)
692 CONFIG_RP9_AS_DIG_PIN();
694 CONFIG_RP8_AS_DIG_PIN();
699 DISABLE_U1TX_ANALOG();
700 DISABLE_U1RX_ANALOG();
701 #elif (HARDWARE_PLATFORM == DEFAULT_DESIGN)
702 #if ( defined(__PIC24E__) || defined(__dsPIC33E__))
704 CONFIG_RP43_AS_DIG_PIN();
708 CONFIG_RP11_AS_DIG_PIN();
714 DISABLE_U1TX_ANALOG();
715 DISABLE_U1RX_ANALOG();
717 #error Unknown hardware platform.
720 #warning UART2 pin mappings not defined. See comments below for more info.
744 u32_brg =
FCY/u32_baudRate;
745 #if (DEFAULT_BRGH2 == 0)
746 if ((u32_brg & 0x0FL) >= 8) u32_brg = u32_brg/16;
747 else u32_brg = u32_brg/16 - 1;
749 if ((brg & 0x03L) >= 2) u32_brg = u32_brg/4;
750 else u32_brg = u32_brg/4 - 1;
755 #if (DEFAULT_BRGH2 == 0)
756 f_brg = (((float)
FCY)/((float) u32_baudRate)/16.0) - 1.0;
758 f_brg = (((float)
FCY)/((float) u32_baudRate)/4.0) - 1.0;
780 (DEFAULT_BRGH2 << 3) |
807 ASSERT(u32_baudRate >= 1000L);
816 while (U2STAbits.PERR || U2STAbits.FERR) {
821 #ifdef UART2_RX_INTERRUPT
823 _U2RXIP = UART2_RX_INTERRUPT_PRIORITY;
826 #ifdef UART2_TX_INTERRUPT
828 _U2TXIP = UART2_TX_INTERRUPT_PRIORITY;
834 #endif // #if (NUM_UARTS >= 2)
878 #if (NUM_UART_MODS >= 3)
904 void checkRxErrorUART3(
void) {
907 if (U3STAbits.PERR) {
911 if (U3STAbits.FERR) {
915 if (U3STAbits.OERR) {
924 #ifdef UART3_TX_INTERRUPT
928 #ifndef UART3_TX_FIFO_SIZE
929 #define UART3_TX_FIFO_SIZE 32 //choose a size
932 #ifndef UART3_TX_INTERRUPT_PRIORITY
933 #define UART3_TX_INTERRUPT_PRIORITY 1
936 volatile uint8_t au8_txFifo3[UART3_TX_FIFO_SIZE];
937 volatile uint16_t u16_txFifo3Head = 0;
938 volatile uint16_t u16_txFifo3Tail = 0;
947 u16_tmp = u16_txFifo3Head;
949 if (u16_tmp == UART3_TX_FIFO_SIZE) u16_tmp = 0;
950 while (u16_tmp == u16_txFifo3Tail)
953 au8_txFifo3[u16_tmp] = u8_c;
954 u16_txFifo3Head = u16_tmp;
958 void _ISR _U3TXInterrupt (
void) {
959 if (u16_txFifo3Head == u16_txFifo3Tail) {
965 if (u16_txFifo3Tail == UART3_TX_FIFO_SIZE)
969 U3TXREG = au8_txFifo3[u16_txFifo3Tail];
981 while (IS_TRANSMIT_BUFFER_FULL_UART3())
987 #ifdef UART3_RX_INTERRUPT
989 #ifndef UART3_RX_FIFO_SIZE
990 #define UART3_RX_FIFO_SIZE 32 //choose a size
993 #ifndef UART3_RX_INTERRUPT_PRIORITY
994 #define UART3_RX_INTERRUPT_PRIORITY 1
997 volatile uint8_t au8_rxFifo3[UART3_RX_FIFO_SIZE];
998 volatile uint16_t u16_rxFifo3Head = 0;
999 volatile uint16_t u16_rxFifo3Tail = 0;
1005 return(u16_rxFifo3Head != u16_rxFifo3Tail);
1013 while (u16_rxFifo3Head == u16_rxFifo3Tail)
1016 if (u16_rxFifo3Tail == UART3_RX_FIFO_SIZE) u16_rxFifo3Tail=0;
1017 return au8_rxFifo3[u16_rxFifo3Tail];
1020 void _ISR _U3RXInterrupt (
void) {
1024 checkRxErrorUART3();
1027 if (u16_rxFifo3Head == UART3_RX_FIFO_SIZE)
1028 u16_rxFifo3Head = 0;
1029 if (u16_rxFifo3Head == u16_rxFifo3Tail) {
1033 au8_rxFifo3[u16_rxFifo3Head] = u8_c;
1041 return(IS_CHAR_READY_UART3());
1052 while (!IS_CHAR_READY_UART3())
1054 checkRxErrorUART3();
1064 #ifndef DEFAULT_BRGH3
1065 #define DEFAULT_BRGH3 DEFAULT_BRGH
1068 #if (DEFAULT_BRGH3 != 0) && (DEFAULT_BRGH3 != 1)
1069 #error Invalid value specified for DEFAULT_BRGH3
1081 void configUART3(
uint32_t u32_baudRate) {
1093 #if (HARDWARE_PLATFORM == EXPLORER16_100P)
1099 #if (HARDWARE_PLATFORM == DANGEROUS_WEB)
1100 CONFIG_RP14_AS_DIG_PIN();
1102 CONFIG_RP15_AS_DIG_PIN();
1104 CONFIG_RP10_AS_DIG_PIN();
1108 DISABLE_U1TX_ANALOG();
1109 DISABLE_U1RX_ANALOG();
1110 #elif (HARDWARE_PLATFORM == STARTER_BOARD_28P)
1111 CONFIG_RP9_AS_DIG_PIN();
1113 CONFIG_RP8_AS_DIG_PIN();
1118 DISABLE_U1TX_ANALOG();
1119 DISABLE_U1RX_ANALOG();
1120 #elif (HARDWARE_PLATFORM == DEFAULT_DESIGN)
1121 #if ( defined(__PIC24E__) || defined(__dsPIC33E__))
1122 CONFIG_U3RX_TO_RP(42);
1123 CONFIG_RP43_AS_DIG_PIN();
1124 CONFIG_U3TX_TO_RP(43);
1126 CONFIG_U3RX_TO_RP(10);
1127 CONFIG_RP11_AS_DIG_PIN();
1128 CONFIG_U3TX_TO_RP(11);
1133 DISABLE_U1TX_ANALOG();
1134 DISABLE_U1RX_ANALOG();
1136 #error Unknown hardware platform.
1139 #warning UART3 pin mappings not defined. See comments below for more info.
1154 U3MODE = (0u << 15);
1163 u32_brg =
FCY/u32_baudRate;
1164 #if (DEFAULT_BRGH3 == 0)
1165 if ((u32_brg & 0x0FL) >= 8) u32_brg = u32_brg/16;
1166 else u32_brg = u32_brg/16 - 1;
1168 if ((brg & 0x03L) >= 2) u32_brg = u32_brg/4;
1169 else u32_brg = u32_brg/4 - 1;
1174 #if (DEFAULT_BRGH3 == 0)
1175 f_brg = (((float)
FCY)/((float) u32_baudRate)/16.0) - 1.0;
1177 f_brg = (((float)
FCY)/((float) u32_baudRate)/4.0) - 1.0;
1199 (DEFAULT_BRGH3 << 3) |
1226 ASSERT(u32_baudRate >= 1000L);
1235 while (U3STAbits.PERR || U3STAbits.FERR) {
1240 #ifdef UART3_RX_INTERRUPT
1242 _U3RXIP = UART3_RX_INTERRUPT_PRIORITY;
1245 #ifdef UART3_TX_INTERRUPT
1247 _U3TXIP = UART3_TX_INTERRUPT_PRIORITY;
1253 #endif // #if (NUM_UARTS >= 3)
1297 #if (NUM_UART_MODS >= 4)
1323 void checkRxErrorUART4(
void) {
1326 if (U4STAbits.PERR) {
1330 if (U4STAbits.FERR) {
1334 if (U4STAbits.OERR) {
1343 #ifdef UART4_TX_INTERRUPT
1347 #ifndef UART4_TX_FIFO_SIZE
1348 #define UART4_TX_FIFO_SIZE 32 //choose a size
1351 #ifndef UART4_TX_INTERRUPT_PRIORITY
1352 #define UART4_TX_INTERRUPT_PRIORITY 1
1355 volatile uint8_t au8_txFifo4[UART4_TX_FIFO_SIZE];
1356 volatile uint16_t u16_txFifo4Head = 0;
1357 volatile uint16_t u16_txFifo4Tail = 0;
1366 u16_tmp = u16_txFifo4Head;
1368 if (u16_tmp == UART4_TX_FIFO_SIZE) u16_tmp = 0;
1369 while (u16_tmp == u16_txFifo4Tail)
1372 au8_txFifo4[u16_tmp] = u8_c;
1373 u16_txFifo4Head = u16_tmp;
1377 void _ISR _U4TXInterrupt (
void) {
1378 if (u16_txFifo4Head == u16_txFifo4Tail) {
1384 if (u16_txFifo4Tail == UART4_TX_FIFO_SIZE)
1385 u16_txFifo4Tail = 0;
1388 U4TXREG = au8_txFifo4[u16_txFifo4Tail];
1400 while (IS_TRANSMIT_BUFFER_FULL_UART4())
1406 #ifdef UART4_RX_INTERRUPT
1408 #ifndef UART4_RX_FIFO_SIZE
1409 #define UART4_RX_FIFO_SIZE 32 //choose a size
1412 #ifndef UART4_RX_INTERRUPT_PRIORITY
1413 #define UART4_RX_INTERRUPT_PRIORITY 1
1416 volatile uint8_t au8_rxFifo4[UART4_RX_FIFO_SIZE];
1417 volatile uint16_t u16_rxFifo4Head = 0;
1418 volatile uint16_t u16_rxFifo4Tail = 0;
1424 return(u16_rxFifo4Head != u16_rxFifo4Tail);
1432 while (u16_rxFifo4Head == u16_rxFifo4Tail)
1435 if (u16_rxFifo4Tail == UART4_RX_FIFO_SIZE) u16_rxFifo4Tail=0;
1436 return au8_rxFifo4[u16_rxFifo4Tail];
1439 void _ISR _U4RXInterrupt (
void) {
1443 checkRxErrorUART4();
1446 if (u16_rxFifo4Head == UART4_RX_FIFO_SIZE)
1447 u16_rxFifo4Head = 0;
1448 if (u16_rxFifo4Head == u16_rxFifo4Tail) {
1452 au8_rxFifo4[u16_rxFifo4Head] = u8_c;
1460 return(IS_CHAR_READY_UART4());
1471 while (!IS_CHAR_READY_UART4())
1473 checkRxErrorUART4();
1483 #ifndef DEFAULT_BRGH4
1484 #define DEFAULT_BRGH4 DEFAULT_BRGH
1487 #if (DEFAULT_BRGH4 != 0) && (DEFAULT_BRGH4 != 1)
1488 #error Invalid value specified for DEFAULT_BRGH4
1500 void configUART4(
uint32_t u32_baudRate) {
1512 #if (HARDWARE_PLATFORM == EXPLORER16_100P)
1518 #if (HARDWARE_PLATFORM == DANGEROUS_WEB)
1519 CONFIG_RP14_AS_DIG_PIN();
1521 CONFIG_RP15_AS_DIG_PIN();
1523 CONFIG_RP10_AS_DIG_PIN();
1527 DISABLE_U1TX_ANALOG();
1528 DISABLE_U1RX_ANALOG();
1529 #elif (HARDWARE_PLATFORM == STARTER_BOARD_28P)
1530 CONFIG_RP9_AS_DIG_PIN();
1532 CONFIG_RP8_AS_DIG_PIN();
1537 DISABLE_U1TX_ANALOG();
1538 DISABLE_U1RX_ANALOG();
1539 #elif (HARDWARE_PLATFORM == DEFAULT_DESIGN)
1540 #if ( defined(__PIC24E__) || defined(__dsPIC33E__))
1541 CONFIG_U4RX_TO_RP(42);
1542 CONFIG_RP43_AS_DIG_PIN();
1543 CONFIG_U4TX_TO_RP(43);
1545 CONFIG_U4RX_TO_RP(10);
1546 CONFIG_RP11_AS_DIG_PIN();
1547 CONFIG_U4TX_TO_RP(11);
1552 DISABLE_U1TX_ANALOG();
1553 DISABLE_U1RX_ANALOG();
1555 #error Unknown hardware platform.
1558 #warning UART4 pin mappings not defined. See comments below for more info.
1573 U4MODE = (0u << 15);
1582 u32_brg =
FCY/u32_baudRate;
1583 #if (DEFAULT_BRGH4 == 0)
1584 if ((u32_brg & 0x0FL) >= 8) u32_brg = u32_brg/16;
1585 else u32_brg = u32_brg/16 - 1;
1587 if ((brg & 0x03L) >= 2) u32_brg = u32_brg/4;
1588 else u32_brg = u32_brg/4 - 1;
1593 #if (DEFAULT_BRGH4 == 0)
1594 f_brg = (((float)
FCY)/((float) u32_baudRate)/16.0) - 1.0;
1596 f_brg = (((float)
FCY)/((float) u32_baudRate)/4.0) - 1.0;
1618 (DEFAULT_BRGH4 << 3) |
1645 ASSERT(u32_baudRate >= 1000L);
1654 while (U4STAbits.PERR || U4STAbits.FERR) {
1659 #ifdef UART4_RX_INTERRUPT
1661 _U4RXIP = UART4_RX_INTERRUPT_PRIORITY;
1664 #ifdef UART4_TX_INTERRUPT
1666 _U4TXIP = UART4_TX_INTERRUPT_PRIORITY;
1672 #endif // #if (NUM_UARTS >= 4)