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esos_pic24_irq.h
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1 /*
2  * "Copyright (c) 2008 Robert B. Reese, Bryan A. Jones, J. W. Bruce ("AUTHORS")"
3  * All rights reserved.
4  * (R. Reese, reese_AT_ece.msstate.edu, Mississippi State University)
5  * (B. A. Jones, bjones_AT_ece.msstate.edu, Mississippi State University)
6  * (J. W. Bruce, jwbruce_AT_ece.msstate.edu, Mississippi State University)
7  *
8  * Permission to use, copy, modify, and distribute this software and its
9  * documentation for any purpose, without fee, and without written agreement is
10  * hereby granted, provided that the above copyright notice, the following
11  * two paragraphs and the authors appear in all copies of this software.
12  *
13  * IN NO EVENT SHALL THE "AUTHORS" BE LIABLE TO ANY PARTY FOR
14  * DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT
15  * OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE "AUTHORS"
16  * HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
17  *
18  * THE "AUTHORS" SPECIFICALLY DISCLAIMS ANY WARRANTIES,
19  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
20  * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS
21  * ON AN "AS IS" BASIS, AND THE "AUTHORS" HAS NO OBLIGATION TO
22  * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS."
23  *
24  * Please maintain this header in its entirety when copying/modifying
25  * these files.
26  *
27  *
28  */
29 
30 /** \file
31  * \brief This file contains macros, prototypes, and definitions for
32  * Microchip PIC24 family specific interrupts on ESOS
33  */
34 
35 /************************************************************************
36  * esos_pic24_irq.h
37  ************************************************************************
38  * User-supplied include file which defines the IRQ which are supported
39  *
40  * NOTE: the file must be consistent with esos_pic24_irq.c which uses
41  * many of these constant to manipulate IRQ registers
42  */
43 
44 #ifndef ESOS_PIC24_IRQ_H
45 #define ESOS_PIC24_IRQ_H
46 
47 #include "esos.h"
48 #include "esos_irq.h"
49 #include "esos_pic24.h"
50 
51 
52 /**
53  * Declaration of an ESOS interrupt.
54  *
55  * This macro is used to declare an ESOS user inerrupt. All ESOS user
56  * interrupt tasks must be declared with this macro.
57  *
58  * \param desc Descriptor of the hardware interrupt
59  *
60  * \note ESOS user interrupts have no arguments passed in and cannot return values.
61  * \note Hardware interrupt descriptors are found in the file <b>esos_<i>hw</i>_irq.h</b>
62  * where <i>hw</i> is the name of the chip for the ESOS port has been written.
63  * \sa ESOS_REGISTER_PIC24_USER_INTERRUPT
64  * \sa ESOS_UNREGISTER_PIC24_USER_INTERRUPT
65  * \sa ESOS_ENABLE_PIC24_USER_INTERRUPT
66  * \sa ESOS_DISABLE_PIC24_USER_INTERRUPT
67  * \sa ESOS_ENABLE_ALL_PIC24_USER_INTERRUPTS
68  * \sa ESOS_DISABLE_ALL_PIC24_USER_INTERRUPTS
69  * \sa ESOS_IS_PIC24_USER_INTERRUPT_ENABLED
70  * \sa ESOS_DOES_PIC24_USER_INTERRUPT_NEED_SERVICING
71  * \sa ESOS_MARK_PIC24_USER_INTERRUPT_SERVICED
72  *
73  * \hideinitializer
74  */
75 #define ESOS_USER_INTERRUPT(desc) __xESOS_USER_ISR(desc)
76 #define __xESOS_USER_ISR(attrib, ivt, ifsr, ifsb, ipcr, ipcb) void _ISRFAST attrib (void)
77 
78 
79 
80 /*
81  * Define the ESOS user IRQ levels here
82  * ESOS-based IRQs will run at IRQ priority levels
83  * 7 and 5.
84  *
85  * NOTE: Any user IRQ with its IRQ priority level at 0 signifies
86  * that the IRQ is not registered with ESOS.
87  */
88 /**
89  * Highest priority user interrupt level on PIC24 Family
90  * \sa ESOS_REGISTER_PIC24_USER_INTERRUPT
91  * \hideinitializer
92  */
93 #define ESOS_USER_IRQ_LEVEL1 6
94 /**
95  * Second-highest priority user interrupt level on PIC24 Family
96  * \sa ESOS_REGISTER_PIC24_USER_INTERRUPT
97  * \hideinitializer
98  */
99 #define ESOS_USER_IRQ_LEVEL2 4
100 /**
101  * Third-highest priority user interrupt level on PIC24 Family
102  * \sa ESOS_REGISTER_PIC24_USER_INTERRUPT
103  * \hideinitializer
104  */
105 #define ESOS_USER_IRQ_LEVEL3 3
106 /**
107  * Lowest priority user interrupt level on PIC24 Family
108  * \sa ESOS_REGISTER_PIC24_USER_INTERRUPT
109  * \hideinitializer
110  */
111 #define ESOS_USER_IRQ_LEVEL4 2
112 
113 #define __ESOS_USER_IRQ_UNREGISTERED 0
114 // this #define is the IPL that will disabled all user IRQs at once
115 #define __ESOS_DISABLE_USER_IRQS_LEVEL ESOS_USER_IRQ_LEVEL2
116 // this #define is the IPL that will enabled all user IRQs at once
117 #define __ESOS_ENABLE_USER_IRQS_LEVEL __ESOS_USER_IRQ_UNREGISTERED
118 
119 /*
120 * IRQ masks for the PIC24HJ32GP202
121 */
122 #if defined(__PIC24HJ32GP202__) || defined(__DOXYGEN__)
123 // MNEMONIC C30 ISR ATTRIB, IVT addr, IFS register, IFS bit, IPC register, IPC bit
124 /**
125  * AD1 Conversion Complete Interrupt (User interrupt descriptor)
126  * \sa ESOS_USER_INTERRUPT
127  * \sa ESOS_REGISTER_PIC24_USER_INTERRUPT
128  * \sa ESOS_UNREGISTER_PIC24_USER_INTERRUPT
129  * \sa ESOS_ENABLE_PIC24_USER_INTERRUPT
130  * \sa ESOS_DISABLE_PIC24_USER_INTERRUPT
131  * \sa ESOS_ENABLE_ALL_PIC24_USER_INTERRUPTS
132  * \sa ESOS_DISABLE_ALL_PIC24_USER_INTERRUPTS
133  * \sa ESOS_IS_PIC24_USER_INTERRUPT_ENABLED
134  * \sa ESOS_DOES_PIC24_USER_INTERRUPT_NEED_SERVICING
135  * \sa ESOS_MARK_PIC24_USER_INTERRUPT_SERVICED
136  * \hideinitializer
137  */
138 #define ESOS_IRQ_PIC24_AD1 _ADC1Interrupt, 0x002E, 0, 13, 3, 4 // AD1 Conversion complete
139 /**
140  * SP1 Event Interrupt (User interrupt descriptor)
141  * \sa ESOS_USER_INTERRUPT
142  * \sa ESOS_REGISTER_PIC24_USER_INTERRUPT
143  * \sa ESOS_UNREGISTER_PIC24_USER_INTERRUPT
144  * \sa ESOS_ENABLE_PIC24_USER_INTERRUPT
145  * \sa ESOS_DISABLE_PIC24_USER_INTERRUPT
146  * \sa ESOS_ENABLE_ALL_PIC24_USER_INTERRUPTS
147  * \sa ESOS_DISABLE_ALL_PIC24_USER_INTERRUPTS
148  * \sa ESOS_IS_PIC24_USER_INTERRUPT_ENABLED
149  * \sa ESOS_DOES_PIC24_USER_INTERRUPT_NEED_SERVICING
150  * \sa ESOS_MARK_PIC24_USER_INTERRUPT_SERVICED
151  * \hideinitializer
152  */
153 #define ESOS_IRQ_PIC24_SPI1 _SPI1Interrupt, 0x0028, 0, 10, 2, 8 // SPI1 event
154 /**
155  * SP1 Exception Event Interrupt (User interrupt descriptor)
156  * \sa ESOS_USER_INTERRUPT
157  * \sa ESOS_REGISTER_PIC24_USER_INTERRUPT
158  * \sa ESOS_UNREGISTER_PIC24_USER_INTERRUPT
159  * \sa ESOS_ENABLE_PIC24_USER_INTERRUPT
160  * \sa ESOS_DISABLE_PIC24_USER_INTERRUPT
161  * \sa ESOS_ENABLE_ALL_PIC24_USER_INTERRUPTS
162  * \sa ESOS_DISABLE_ALL_PIC24_USER_INTERRUPTS
163  * \sa ESOS_IS_PIC24_USER_INTERRUPT_ENABLED
164  * \sa ESOS_DOES_PIC24_USER_INTERRUPT_NEED_SERVICING
165  * \sa ESOS_MARK_PIC24_USER_INTERRUPT_SERVICED
166  * \hideinitializer
167  */
168 #define ESOS_IRQ_PIC24_SPI1E _SPI1ErrInterrupt, 0x0026, 0, 9, 2, 4 // SPI1 (exception) fault event
169 /**
170  * Timer 3 expiration Interrupt (User interrupt descriptor)
171  * \sa ESOS_USER_INTERRUPT
172  * \sa ESOS_REGISTER_PIC24_USER_INTERRUPT
173  * \sa ESOS_UNREGISTER_PIC24_USER_INTERRUPT
174  * \sa ESOS_ENABLE_PIC24_USER_INTERRUPT
175  * \sa ESOS_DISABLE_PIC24_USER_INTERRUPT
176  * \sa ESOS_ENABLE_ALL_PIC24_USER_INTERRUPTS
177  * \sa ESOS_DISABLE_ALL_PIC24_USER_INTERRUPTS
178  * \sa ESOS_IS_PIC24_USER_INTERRUPT_ENABLED
179  * \sa ESOS_DOES_PIC24_USER_INTERRUPT_NEED_SERVICING
180  * \sa ESOS_MARK_PIC24_USER_INTERRUPT_SERVICED
181  * \hideinitializer
182  */
183 #define ESOS_IRQ_PIC24_T3 _T3Interrupt, 0x0024, 0, 8, 2, 0 // Timer 3
184 /**
185  * Timer 2 expiration Interrupt (User interrupt descriptor)
186  * \sa ESOS_USER_INTERRUPT
187  * \sa ESOS_REGISTER_PIC24_USER_INTERRUPT
188  * \sa ESOS_UNREGISTER_PIC24_USER_INTERRUPT
189  * \sa ESOS_ENABLE_PIC24_USER_INTERRUPT
190  * \sa ESOS_DISABLE_PIC24_USER_INTERRUPT
191  * \sa ESOS_ENABLE_ALL_PIC24_USER_INTERRUPTS
192  * \sa ESOS_DISABLE_ALL_PIC24_USER_INTERRUPTS
193  * \sa ESOS_IS_PIC24_USER_INTERRUPT_ENABLED
194  * \sa ESOS_DOES_PIC24_USER_INTERRUPT_NEED_SERVICING
195  * \sa ESOS_MARK_PIC24_USER_INTERRUPT_SERVICED
196  * \hideinitializer
197  */
198 #define ESOS_IRQ_PIC24_T2 _T2Interrupt, 0x0022, 0, 7, 1, 12 // Timer 2
199 /**
200  * Output Compare Channel 2 Interrupt (User interrupt descriptor)
201  * \sa ESOS_USER_INTERRUPT
202  * \sa ESOS_REGISTER_PIC24_USER_INTERRUPT
203  * \sa ESOS_UNREGISTER_PIC24_USER_INTERRUPT
204  * \sa ESOS_ENABLE_PIC24_USER_INTERRUPT
205  * \sa ESOS_DISABLE_PIC24_USER_INTERRUPT
206  * \sa ESOS_ENABLE_ALL_PIC24_USER_INTERRUPTS
207  * \sa ESOS_DISABLE_ALL_PIC24_USER_INTERRUPTS
208  * \sa ESOS_IS_PIC24_USER_INTERRUPT_ENABLED
209  * \sa ESOS_DOES_PIC24_USER_INTERRUPT_NEED_SERVICING
210  * \sa ESOS_MARK_PIC24_USER_INTERRUPT_SERVICED
211  * \hideinitializer
212  */
213 #define ESOS_IRQ_PIC24_OC2 _OC2Interrupt, 0x0020, 0, 6, 1, 8 // Output compare channel 2
214 /**
215  * Input Capture Channel 2 Interrupt (User interrupt descriptor)
216  * \sa ESOS_USER_INTERRUPT
217  * \sa ESOS_REGISTER_PIC24_USER_INTERRUPT
218  * \sa ESOS_UNREGISTER_PIC24_USER_INTERRUPT
219  * \sa ESOS_ENABLE_PIC24_USER_INTERRUPT
220  * \sa ESOS_DISABLE_PIC24_USER_INTERRUPT
221  * \sa ESOS_ENABLE_ALL_PIC24_USER_INTERRUPTS
222  * \sa ESOS_DISABLE_ALL_PIC24_USER_INTERRUPTS
223  * \sa ESOS_IS_PIC24_USER_INTERRUPT_ENABLED
224  * \sa ESOS_DOES_PIC24_USER_INTERRUPT_NEED_SERVICING
225  * \sa ESOS_MARK_PIC24_USER_INTERRUPT_SERVICED
226  * \hideinitializer
227  */
228 #define ESOS_IRQ_PIC24_IC2 _IC2Interrupt, 0x001E, 0, 5, 1, 4 // Input capture channel 2
229 /**
230  * Output Compare Channel 1 Interrupt (User interrupt descriptor)
231  * \sa ESOS_USER_INTERRUPT
232  * \sa ESOS_REGISTER_PIC24_USER_INTERRUPT
233  * \sa ESOS_UNREGISTER_PIC24_USER_INTERRUPT
234  * \sa ESOS_ENABLE_PIC24_USER_INTERRUPT
235  * \sa ESOS_DISABLE_PIC24_USER_INTERRUPT
236  * \sa ESOS_ENABLE_ALL_PIC24_USER_INTERRUPTS
237  * \sa ESOS_DISABLE_ALL_PIC24_USER_INTERRUPTS
238  * \sa ESOS_IS_PIC24_USER_INTERRUPT_ENABLED
239  * \sa ESOS_DOES_PIC24_USER_INTERRUPT_NEED_SERVICING
240  * \sa ESOS_MARK_PIC24_USER_INTERRUPT_SERVICED
241  * \hideinitializer
242  */
243 #define ESOS_IRQ_PIC24_OC1 _OC1Interrupt, 0x0018, 0, 2, 0, 8 // Output compare channel 1
244 
245 /**
246  * Input Capture Channel 1 Interrupt (User interrupt descriptor)
247  * \sa ESOS_USER_INTERRUPT
248  * \sa ESOS_REGISTER_PIC24_USER_INTERRUPT
249  * \sa ESOS_UNREGISTER_PIC24_USER_INTERRUPT
250  * \sa ESOS_ENABLE_PIC24_USER_INTERRUPT
251  * \sa ESOS_DISABLE_PIC24_USER_INTERRUPT
252  * \sa ESOS_ENABLE_ALL_PIC24_USER_INTERRUPTS
253  * \sa ESOS_DISABLE_ALL_PIC24_USER_INTERRUPTS
254  * \sa ESOS_IS_PIC24_USER_INTERRUPT_ENABLED
255  * \sa ESOS_DOES_PIC24_USER_INTERRUPT_NEED_SERVICING
256  * \sa ESOS_MARK_PIC24_USER_INTERRUPT_SERVICED
257  * \hideinitializer
258  */
259 #define ESOS_IRQ_PIC24_IC1 _IC1Interrupt, 0x0016, 0, 1, 0, 4 // Input capture channel 1
260 /**
261  * External IRQ 0 Interrupt (User interrupt descriptor)
262  * \sa ESOS_USER_INTERRUPT
263  * \sa ESOS_REGISTER_PIC24_USER_INTERRUPT
264  * \sa ESOS_UNREGISTER_PIC24_USER_INTERRUPT
265  * \sa ESOS_ENABLE_PIC24_USER_INTERRUPT
266  * \sa ESOS_DISABLE_PIC24_USER_INTERRUPT
267  * \sa ESOS_ENABLE_ALL_PIC24_USER_INTERRUPTS
268  * \sa ESOS_DISABLE_ALL_PIC24_USER_INTERRUPTS
269  * \sa ESOS_IS_PIC24_USER_INTERRUPT_ENABLED
270  * \sa ESOS_DOES_PIC24_USER_INTERRUPT_NEED_SERVICING
271  * \sa ESOS_MARK_PIC24_USER_INTERRUPT_SERVICED
272  * \hideinitializer
273  */
274 #define ESOS_IRQ_PIC24_INT0 _INT0Interrupt, 0x0014, 0, 0, 0, 0 // external interrupt 0
275 /**
276  * External IRQ 2 Interrupt (User interrupt descriptor)
277  * \sa ESOS_USER_INTERRUPT
278  * \sa ESOS_REGISTER_PIC24_USER_INTERRUPT
279  * \sa ESOS_UNREGISTER_PIC24_USER_INTERRUPT
280  * \sa ESOS_ENABLE_PIC24_USER_INTERRUPT
281  * \sa ESOS_DISABLE_PIC24_USER_INTERRUPT
282  * \sa ESOS_ENABLE_ALL_PIC24_USER_INTERRUPTS
283  * \sa ESOS_DISABLE_ALL_PIC24_USER_INTERRUPTS
284  * \sa ESOS_IS_PIC24_USER_INTERRUPT_ENABLED
285  * \sa ESOS_DOES_PIC24_USER_INTERRUPT_NEED_SERVICING
286  * \sa ESOS_MARK_PIC24_USER_INTERRUPT_SERVICED
287  * \hideinitializer
288  */
289 #define ESOS_IRQ_PIC24_INT2 _INT2Interrupt, 0x004E, 1, 13, 7, 4 // external interrupt 2
290 
291 /**
292  * Input Capture Channel 8 Interrupt (User interrupt descriptor)
293  * \sa ESOS_USER_INTERRUPT
294  * \sa ESOS_REGISTER_PIC24_USER_INTERRUPT
295  * \sa ESOS_UNREGISTER_PIC24_USER_INTERRUPT
296  * \sa ESOS_ENABLE_PIC24_USER_INTERRUPT
297  * \sa ESOS_DISABLE_PIC24_USER_INTERRUPT
298  * \sa ESOS_ENABLE_ALL_PIC24_USER_INTERRUPTS
299  * \sa ESOS_DISABLE_ALL_PIC24_USER_INTERRUPTS
300  * \sa ESOS_IS_PIC24_USER_INTERRUPT_ENABLED
301  * \sa ESOS_DOES_PIC24_USER_INTERRUPT_NEED_SERVICING
302  * \sa ESOS_MARK_PIC24_USER_INTERRUPT_SERVICED
303  * \hideinitializer
304  */
305 #define ESOS_IRQ_PIC24_IC8 _IC8Interrupt, 0x0042, 1, 7, 5, 12 // Input capture channel 8
306 /**
307  * Input Capture Channel 7 Interrupt (User interrupt descriptor)
308  * \sa ESOS_USER_INTERRUPT
309  * \sa ESOS_REGISTER_PIC24_USER_INTERRUPT
310  * \sa ESOS_UNREGISTER_PIC24_USER_INTERRUPT
311  * \sa ESOS_ENABLE_PIC24_USER_INTERRUPT
312  * \sa ESOS_DISABLE_PIC24_USER_INTERRUPT
313  * \sa ESOS_ENABLE_ALL_PIC24_USER_INTERRUPTS
314  * \sa ESOS_DISABLE_ALL_PIC24_USER_INTERRUPTS
315  * \sa ESOS_IS_PIC24_USER_INTERRUPT_ENABLED
316  * \sa ESOS_DOES_PIC24_USER_INTERRUPT_NEED_SERVICING
317  * \sa ESOS_MARK_PIC24_USER_INTERRUPT_SERVICED
318  * \hideinitializer
319  */
320 #define ESOS_IRQ_PIC24_IC7 _IC7Interrupt, 0x0040, 1, 6, 5, 8 // Input capture channel 7
321 /**
322  * External IRQ 1 Interrupt (User interrupt descriptor)
323  * \sa ESOS_USER_INTERRUPT
324  * \sa ESOS_REGISTER_PIC24_USER_INTERRUPT
325  * \sa ESOS_UNREGISTER_PIC24_USER_INTERRUPT
326  * \sa ESOS_ENABLE_PIC24_USER_INTERRUPT
327  * \sa ESOS_DISABLE_PIC24_USER_INTERRUPT
328  * \sa ESOS_ENABLE_ALL_PIC24_USER_INTERRUPTS
329  * \sa ESOS_DISABLE_ALL_PIC24_USER_INTERRUPTS
330  * \sa ESOS_IS_PIC24_USER_INTERRUPT_ENABLED
331  * \sa ESOS_DOES_PIC24_USER_INTERRUPT_NEED_SERVICING
332  * \sa ESOS_MARK_PIC24_USER_INTERRUPT_SERVICED
333  * \hideinitializer
334  */
335 #define ESOS_IRQ_PIC24_INT1 _INT1Interrupt, 0x003C, 1, 4, 5, 0 // external interrupt 1
336 /**
337  * Input Change Notification Interrupt (User interrupt descriptor)
338  * \sa ESOS_USER_INTERRUPT
339  * \sa ESOS_REGISTER_PIC24_USER_INTERRUPT
340  * \sa ESOS_UNREGISTER_PIC24_USER_INTERRUPT
341  * \sa ESOS_ENABLE_PIC24_USER_INTERRUPT
342  * \sa ESOS_DISABLE_PIC24_USER_INTERRUPT
343  * \sa ESOS_ENABLE_ALL_PIC24_USER_INTERRUPTS
344  * \sa ESOS_DISABLE_ALL_PIC24_USER_INTERRUPTS
345  * \sa ESOS_IS_PIC24_USER_INTERRUPT_ENABLED
346  * \sa ESOS_DOES_PIC24_USER_INTERRUPT_NEED_SERVICING
347  * \sa ESOS_MARK_PIC24_USER_INTERRUPT_SERVICED
348  * \hideinitializer
349  */
350 #define ESOS_IRQ_PIC24_CN _CNInterrupt, 0x003A, 1, 3, 4, 12 // input change notification
351 /**
352  * I2C1 Master Event Interrupt (User interrupt descriptor)
353  * \sa ESOS_USER_INTERRUPT
354  * \sa ESOS_REGISTER_PIC24_USER_INTERRUPT
355  * \sa ESOS_UNREGISTER_PIC24_USER_INTERRUPT
356  * \sa ESOS_ENABLE_PIC24_USER_INTERRUPT
357  * \sa ESOS_DISABLE_PIC24_USER_INTERRUPT
358  * \sa ESOS_ENABLE_ALL_PIC24_USER_INTERRUPTS
359  * \sa ESOS_DISABLE_ALL_PIC24_USER_INTERRUPTS
360  * \sa ESOS_IS_PIC24_USER_INTERRUPT_ENABLED
361  * \sa ESOS_DOES_PIC24_USER_INTERRUPT_NEED_SERVICING
362  * \sa ESOS_MARK_PIC24_USER_INTERRUPT_SERVICED
363  * \hideinitializer
364  */
365 #define ESOS_IRQ_PIC24_MI2C1 _MI2C1Interrupt, 0x0036, 1, 1, 4, 4 // I2C1 Master event
366 /**
367  * I2C1 Slave Event Interrupt (User interrupt descriptor)
368  * \sa ESOS_USER_INTERRUPT
369  * \sa ESOS_REGISTER_PIC24_USER_INTERRUPT
370  * \sa ESOS_UNREGISTER_PIC24_USER_INTERRUPT
371  * \sa ESOS_ENABLE_PIC24_USER_INTERRUPT
372  * \sa ESOS_DISABLE_PIC24_USER_INTERRUPT
373  * \sa ESOS_ENABLE_ALL_PIC24_USER_INTERRUPTS
374  * \sa ESOS_DISABLE_ALL_PIC24_USER_INTERRUPTS
375  * \sa ESOS_IS_PIC24_USER_INTERRUPT_ENABLED
376  * \sa ESOS_DOES_PIC24_USER_INTERRUPT_NEED_SERVICING
377  * \sa ESOS_MARK_PIC24_USER_INTERRUPT_SERVICED
378  * \hideinitializer
379  */
380 #define ESOS_IRQ_PIC24_SI2C1 _SI2C1Interrupt, 0x0034, 1, 0, 4, 0 // I2C1 slave event
381 
382 // if the user is __NOT__ using the built-in ESOS comm system but __IS__ using user IRQs, then
383 // we should define the UART IRQs for their use
384 // #ifndef _ESOS_PIC24_RS232_H
385 #if !defined(_ESOS_PIC24_RS232_H) || defined(__DOXYGEN__)
386 /**
387  * UART1 TX Event Interrupt (User interrupt descriptor)
388  * \note Only defined if ESOS is built <em>without</em> the communications subsystem.
389  * \sa ESOS_USER_INTERRUPT
390  * \sa ESOS_REGISTER_PIC24_USER_INTERRUPT
391  * \sa ESOS_UNREGISTER_PIC24_USER_INTERRUPT
392  * \sa ESOS_ENABLE_PIC24_USER_INTERRUPT
393  * \sa ESOS_DISABLE_PIC24_USER_INTERRUPT
394  * \sa ESOS_ENABLE_ALL_PIC24_USER_INTERRUPTS
395  * \sa ESOS_DISABLE_ALL_PIC24_USER_INTERRUPTS
396  * \sa ESOS_IS_PIC24_USER_INTERRUPT_ENABLED
397  * \sa ESOS_DOES_PIC24_USER_INTERRUPT_NEED_SERVICING
398  * \sa ESOS_MARK_PIC24_USER_INTERRUPT_SERVICED
399  * \hideinitializer
400  */
401 #define ESOS_IRQ_PIC24_U1TX _U1TXInterrupt, 0x002C, 0, 12, 3, 0 // UART1 TX event
402 /**
403  * UART1 RX Event Interrupt (User interrupt descriptor)
404  * \sa ESOS_USER_INTERRUPT
405  * \sa ESOS_REGISTER_PIC24_USER_INTERRUPT
406  * \sa ESOS_UNREGISTER_PIC24_USER_INTERRUPT
407  * \sa ESOS_ENABLE_PIC24_USER_INTERRUPT
408  * \sa ESOS_DISABLE_PIC24_USER_INTERRUPT
409  * \sa ESOS_ENABLE_ALL_PIC24_USER_INTERRUPTS
410  * \sa ESOS_DISABLE_ALL_PIC24_USER_INTERRUPTS
411  * \sa ESOS_IS_PIC24_USER_INTERRUPT_ENABLED
412  * \sa ESOS_DOES_PIC24_USER_INTERRUPT_NEED_SERVICING
413  * \sa ESOS_MARK_PIC24_USER_INTERRUPT_SERVICED
414  * \note Only defined if ESOS is built <em>without</em> the communications subsystem.
415  * \hideinitializer
416  */
417 #define ESOS_IRQ_PIC24_U1RX _U1RXInterrupt, 0x002A, 0, 11, 2, 12 // UART1 RX event
418 
419 /**
420  * UART1 Error Event Interrupt (User interrupt descriptor)
421  * \sa ESOS_USER_INTERRUPT
422  * \sa ESOS_REGISTER_PIC24_USER_INTERRUPT
423  * \sa ESOS_UNREGISTER_PIC24_USER_INTERRUPT
424  * \sa ESOS_ENABLE_PIC24_USER_INTERRUPT
425  * \sa ESOS_DISABLE_PIC24_USER_INTERRUPT
426  * \sa ESOS_ENABLE_ALL_PIC24_USER_INTERRUPTS
427  * \sa ESOS_DISABLE_ALL_PIC24_USER_INTERRUPTS
428  * \sa ESOS_IS_PIC24_USER_INTERRUPT_ENABLED
429  * \sa ESOS_DOES_PIC24_USER_INTERRUPT_NEED_SERVICING
430  * \sa ESOS_MARK_PIC24_USER_INTERRUPT_SERVICED
431  * \note Only defined if ESOS is built <em>without</em> the communications subsystem.
432  * \hideinitializer
433  */
434 #define ESOS_IRQ_PIC24_U1E _U1ErrInterrupt, 0x0096, 4, 1, 16, 4 // UART1 Error event
435 
436 #endif // end of UART1 constants
437 
438 #endif // __PIC24HJ32GP202__
439 
440 /*
441  * MACROs COMMON TO ALL PIC24 PROCESSORS
442  */
443 
444 #define __GET_IRQ_ATTRIB(Q) __xGET_IRQ_ATTRIB(Q)
445 #define __GET_IVTQ(Q) __xGET_IVT(Q)
446 #define __GET_IFS_NUM(Q) __xGET_IFS_NUM(Q)
447 #define __GET_IFS_BITNUM(Q) __xGET_IFS_BITNUM(Q)
448 #define __GET_IEC_NUM(Q) __xGET_IFS_NUM(Q)
449 #define __GET_IEC_BITNUM(Q) __xGET_IFS_BITNUM(Q)
450 #define __GET_IPC_NUM(Q) __xGET_IPC_NUM(Q)
451 #define __GET_IPC_BITNUM(Q) __xGET_IPC_BITNUM(Q)
452 
453 #define __xGET_IRQ_ATTRIB(attrib, ivt, ifsr, ifsb, ipcr, ipcb) attrib
454 #define __xGET_IVT(attrib, ivt, ifsr, ifsb, ipcr, ipcb) ivt
455 #define __xGET_IFS_NUM(attrib, ivt, ifsr, ifsb, ipcr, ipcb) ifsr
456 #define __xGET_IFS_BITNUM(attrib, ivt, ifsr, ifsb, ipcr, ipcb) ifsb
457 #define __xGET_IEC_NUM(attrib, ivt, ifsr, ifsb, ipcr, ipcb) ifsr
458 #define __xGET_IEC_BITNUM(attrib, ivt, ifsr, ifsb, ipcr, ipcb) ifsb
459 #define __xGET_IPC_NUM(attrib, ivt, ifsr, ifsb, ipcr, ipcb) ipcr
460 #define __xGET_IPC_BITNUM(attrib, ivt, ifsr, ifsb, ipcr, ipcb) ipcb
461 
462 
463 // this macro gets the IRQ's IPL number from its corresponding IPC register
464 #define __GET_IPL_FROM_IPCX(Q) ((*(&IPC0+(__xGET_IPC_NUM(Q))) >> __xGET_IPC_BITNUM(Q))&0x7)
465 
466 // this macro tests the IRQ's IPL number from its corresponding IPC register
467 // against a value
468 #define __IS_IPL_FROM_IPCX(Q, val) ((__GET_IPL_FROM_IPCX(Q))==(val))
469 
470 // this macro sets the IRQ's IPL number in its corresponding IPC register
471 #define __PUT_IPL_INTO_IPCX(ipc,ipcb,ipl) \
472  do { \
473  BIT_CLEAR_MASK( *(&IPC0+(ipc)), 0x07<<ipcb) + (ipl<<ipcb); \
474  *(&IPC0+ipc) += (ipl<<ipcb); \
475  }while(0)
476 
477 /**
478 * Unregisters the user interrupt denoted by the interrupt descriptor
479 * \param desc Descriptor of the hardware interrupt
480 * \note Hardware interrupt descriptors are found in the file <b>esos_<i>hw</i>_irq.h</b>
481 * where <i>hw</i> is the name of the chip for the ESOS port has been written.
482 * \hideinitializer
483  * \sa ESOS_USER_INTERRUPT
484  * \sa ESOS_REGISTER_PIC24_USER_INTERRUPT
485  * \sa ESOS_ENABLE_PIC24_USER_INTERRUPT
486  * \sa ESOS_DISABLE_PIC24_USER_INTERRUPT
487  * \sa ESOS_ENABLE_ALL_PIC24_USER_INTERRUPTS
488  * \sa ESOS_DISABLE_ALL_PIC24_USER_INTERRUPTS
489  * \sa ESOS_IS_PIC24_USER_INTERRUPT_ENABLED
490  * \sa ESOS_DOES_PIC24_USER_INTERRUPT_NEED_SERVICING
491  * \sa ESOS_MARK_PIC24_USER_INTERRUPT_SERVICED
492  */
493 #define ESOS_UNREGISTER_PIC24_USER_INTERRUPT(desc) __xUNREGISTER_PIC24_USER_INTERRUPT(desc)
494 #define __xUNREGISTER_PIC24_USER_INTERRUPT(attrib, ivt, ifsr, ifsb, ipcr, ipcb) \
495  do{ \
496  __xDISABLE_PIC24_USER_INTERRUPT(attrib, ivt, ifsr, ifsb, ipcr, ipcb); \
497  __PUT_IPL_INTO_IPCX(ipcr,ipcb, __ESOS_USER_IRQ_UNREGISTERED); \
498  }while(0)
499 
500 
501 /**
502 * Registers the user interrupt denoted by the interrupt descriptor
503 * \param desc Descriptor of the hardware interrupt
504 * \param ipl Interrupt Priority Level (IPL) for the interrupt being registered
505 * \param p2f Pointer to function to serve as the ISR. Function must have <em>void</em>
506 * arguments and return <em>void</em>
507 * \note Hardware interrupt descriptors are found in the file <b>esos_<i>hw</i>_irq.h</b>
508 * where <i>hw</i> is the name of the chip for the ESOS port has been written.
509 * \hideinitializer
510  * \sa ESOS_USER_INTERRUPT
511  * \sa ESOS_UNREGISTER_PIC24_USER_INTERRUPT
512  * \sa ESOS_ENABLE_PIC24_USER_INTERRUPT
513  * \sa ESOS_DISABLE_PIC24_USER_INTERRUPT
514  * \sa ESOS_ENABLE_ALL_PIC24_USER_INTERRUPTS
515  * \sa ESOS_DISABLE_ALL_PIC24_USER_INTERRUPTS
516  * \sa ESOS_IS_PIC24_USER_INTERRUPT_ENABLED
517  * \sa ESOS_DOES_PIC24_USER_INTERRUPT_NEED_SERVICING
518  * \sa ESOS_MARK_PIC24_USER_INTERRUPT_SERVICED
519  */
520 #define ESOS_REGISTER_PIC24_USER_INTERRUPT(desc, ipl, p2f) __xREGISTER_PIC24_USER_INTERRUPT(desc, ipl, p2f)
521 #define __xREGISTER_PIC24_USER_INTERRUPT(attrib, ivt, ifsr, ifsb, ipcr, ipcb, ipl, p2f) \
522  do { \
523  __xDISABLE_PIC24_USER_INTERRUPT(attrib, ivt, ifsr, ifsb, ipcr, ipcb); \
524  __PUT_IPL_INTO_IPCX(ipcr, ipcb, ipl); \
525  }while(0)
526 
527 /**
528 * Disables all registered user interrupts.
529 * \note This function does <em>NOT</em> disable all interrupts. Interrupts used by
530 * ESOS will continue to function.
531  * \sa ESOS_USER_INTERRUPT
532  * \sa ESOS_REGISTER_PIC24_USER_INTERRUPT
533  * \sa ESOS_UNREGISTER_PIC24_USER_INTERRUPT
534  * \sa ESOS_ENABLE_PIC24_USER_INTERRUPT
535  * \sa ESOS_DISABLE_PIC24_USER_INTERRUPT
536  * \sa ESOS_ENABLE_ALL_PIC24_USER_INTERRUPTS
537  * \sa ESOS_IS_PIC24_USER_INTERRUPT_ENABLED
538  * \sa ESOS_DOES_PIC24_USER_INTERRUPT_NEED_SERVICING
539  * \sa ESOS_MARK_PIC24_USER_INTERRUPT_SERVICED
540 * \hideinitializer
541 */
542 #define ESOS_DISABLE_ALL_PIC24_USER_INTERRUPTS() SET_CPU_IPL(__ESOS_DISABLE_USER_IRQS_LEVEL)
543 
544 /**
545 * Enables all registered user interrupts.
546 * \note Does not affect interrupts used by ESOS
547  * \sa ESOS_USER_INTERRUPT
548  * \sa ESOS_REGISTER_PIC24_USER_INTERRUPT
549  * \sa ESOS_UNREGISTER_PIC24_USER_INTERRUPT
550  * \sa ESOS_ENABLE_PIC24_USER_INTERRUPT
551  * \sa ESOS_DISABLE_PIC24_USER_INTERRUPT
552  * \sa ESOS_DISABLE_ALL_PIC24_USER_INTERRUPTS
553  * \sa ESOS_IS_PIC24_USER_INTERRUPT_ENABLED
554  * \sa ESOS_DOES_PIC24_USER_INTERRUPT_NEED_SERVICING
555  * \sa ESOS_MARK_PIC24_USER_INTERRUPT_SERVICED
556 * \hideinitializer
557 */
558 #define ESOS_ENABLE_ALL_PIC24_USER_INTERRUPTS() SET_CPU_IPL(__ESOS_ENABLE_USER_IRQS_LEVEL)
559 
560 /**
561 * Queries the enabled state of user interrupt denoted by the interrupt descriptor
562 * \param desc Descriptor of the hardware interrupt
563 * \retval TRUE If the user interrupt is currently enabled
564 * \retval FALSE If the user interrupt is currently disabled
565 * \note Hardware interrupt descriptors are found in the file <b>esos_<i>hw</i>_irq.h</b>
566 * where <i>hw</i> is the name of the chip for the ESOS port has been written.
567 * \hideinitializer
568  * \sa ESOS_USER_INTERRUPT
569  * \sa ESOS_REGISTER_PIC24_USER_INTERRUPT
570  * \sa ESOS_UNREGISTER_PIC24_USER_INTERRUPT
571  * \sa ESOS_ENABLE_PIC24_USER_INTERRUPT
572  * \sa ESOS_DISABLE_PIC24_USER_INTERRUPT
573  * \sa ESOS_ENABLE_ALL_PIC24_USER_INTERRUPTS
574  * \sa ESOS_DISABLE_ALL_PIC24_USER_INTERRUPTS
575  * \sa ESOS_DOES_PIC24_USER_INTERRUPT_NEED_SERVICING
576  * \sa ESOS_MARK_PIC24_USER_INTERRUPT_SERVICED
577  */
578 #define ESOS_IS_PIC24_USER_INTERRUPT_ENABLED(desc) __xIS_PIC24_USER_INTERRUPT_ENABLED(desc)
579 #define __xIS_PIC24_USER_INTERRUPT_ENABLED(attrib, ivt, ifsr, ifsb, ipcr, ipcb) IS_BIT_SET(*(&IEC0+ifsr),ifsb)
580 
581 /**
582 * Queries the "flag" state of user interrupt denoted by the interrupt descriptor
583 * \param desc Descriptor of the hardware interrupt
584 * \retval TRUE If the user interrupt is needs to be serviced
585 * \retval FALSE Otherwise
586 * \note Hardware interrupt descriptors are found in the file <b>esos_<i>hw</i>_irq.h</b>
587 * where <i>hw</i> is the name of the chip for the ESOS port has been written.
588 * \hideinitializer
589  * \sa ESOS_USER_INTERRUPT
590  * \sa ESOS_REGISTER_PIC24_USER_INTERRUPT
591  * \sa ESOS_UNREGISTER_PIC24_USER_INTERRUPT
592  * \sa ESOS_ENABLE_PIC24_USER_INTERRUPT
593  * \sa ESOS_DISABLE_PIC24_USER_INTERRUPT
594  * \sa ESOS_ENABLE_ALL_PIC24_USER_INTERRUPTS
595  * \sa ESOS_DISABLE_ALL_PIC24_USER_INTERRUPTS
596  * \sa ESOS_IS_PIC24_USER_INTERRUPT_ENABLED
597  * \sa ESOS_MARK_PIC24_USER_INTERRUPT_SERVICED
598 */
599 #define ESOS_DOES_PIC24_USER_INTERRUPT_NEED_SERVICING(desc) __xDOES_PIC24_USER_INTERRUPT_NEED_SERVICING(desc)
600 #define __xDOES_PIC24_USER_INTERRUPT_NEED_SERVICING(attrib, ivt, ifsr, ifsb, ipcr, ipcb) IS_BIT_SET(*(&IFS0+ifsr), ifsb)
601 
602 /**
603 * Tells ESOS to mark the user interrupt denoted by the interrupt descriptor as being serviced
604 * \param desc Descriptor of the hardware interrupt
605 * \note Hardware interrupt descriptors are found in the file <b>esos_<i>hw</i>_irq.h</b>
606 * where <i>hw</i> is the name of the chip for the ESOS port has been written.
607 * \hideinitializer
608  * \sa ESOS_USER_INTERRUPT
609  * \sa ESOS_REGISTER_PIC24_USER_INTERRUPT
610  * \sa ESOS_UNREGISTER_PIC24_USER_INTERRUPT
611  * \sa ESOS_ENABLE_PIC24_USER_INTERRUPT
612  * \sa ESOS_DISABLE_PIC24_USER_INTERRUPT
613  * \sa ESOS_ENABLE_ALL_PIC24_USER_INTERRUPTS
614  * \sa ESOS_DISABLE_ALL_PIC24_USER_INTERRUPTS
615  * \sa ESOS_IS_PIC24_USER_INTERRUPT_ENABLED
616  * \sa ESOS_MARK_PIC24_USER_INTERRUPT_SERVICED
617 */
618 #define ESOS_MARK_PIC24_USER_INTERRUPT_SERVICED(desc) __xMARK_PIC24_USER_INTERRUPT_SERVICED(desc)
619 #define __xMARK_PIC24_USER_INTERRUPT_SERVICED(attrib, ivt, ifsr, ifsb, ipcr, ipcb) BIT_CLEAR(*(&IFS0+ifsr),ifsb)
620 
621 /**
622 * Enables the user interrupt denoted by the interrupt descriptor
623 * \param desc Descriptor of the hardware interrupt
624 * \note Hardware interrupt descriptors are found in the file <b>esos_<i>hw</i>_irq.h</b>
625 * where <i>hw</i> is the name of the chip for the ESOS port has been written.
626 * \hideinitializer
627  * \sa ESOS_USER_INTERRUPT
628  * \sa ESOS_REGISTER_PIC24_USER_INTERRUPT
629  * \sa ESOS_UNREGISTER_PIC24_USER_INTERRUPT
630  * \sa ESOS_DISABLE_PIC24_USER_INTERRUPT
631  * \sa ESOS_ENABLE_ALL_PIC24_USER_INTERRUPTS
632  * \sa ESOS_DISABLE_ALL_PIC24_USER_INTERRUPTS
633  * \sa ESOS_IS_PIC24_USER_INTERRUPT_ENABLED
634  * \sa ESOS_DOES_PIC24_USER_INTERRUPT_NEED_SERVICING
635  * \sa ESOS_MARK_PIC24_USER_INTERRUPT_SERVICED
636  */
637 #define ESOS_ENABLE_PIC24_USER_INTERRUPT(desc) __xENABLE_PIC24_USER_INTERRUPT(desc)
638 #define __xENABLE_PIC24_USER_INTERRUPT(attrib, ivt, ifsr, ifsb, ipcr, ipcb) BIT_SET(*(&IEC0+ifsr), ifsb)
639 
640 /**
641 * Disables the user interrupt denoted by the interrupt descriptor
642 * \param desc Descriptor of the hardware interrupt
643 * \note Hardware interrupt descriptors are found in the file <b>esos_<i>hw</i>_irq.h</b>
644 * where <i>hw</i> is the name of the chip for the ESOS port has been written.
645 * \hideinitializer
646  * \sa ESOS_USER_INTERRUPT
647  * \sa ESOS_REGISTER_PIC24_USER_INTERRUPT
648  * \sa ESOS_UNREGISTER_PIC24_USER_INTERRUPT
649  * \sa ESOS_ENABLE_PIC24_USER_INTERRUPT
650  * \sa ESOS_ENABLE_ALL_PIC24_USER_INTERRUPTS
651  * \sa ESOS_DISABLE_ALL_PIC24_USER_INTERRUPTS
652  * \sa ESOS_IS_PIC24_USER_INTERRUPT_ENABLED
653  * \sa ESOS_DOES_PIC24_USER_INTERRUPT_NEED_SERVICING
654  * \sa ESOS_MARK_PIC24_USER_INTERRUPT_SERVICED
655  */
656 #define ESOS_DISABLE_PIC24_USER_INTERRUPT(desc) __xDISABLE_PIC24_USER_INTERRUPT(desc)
657 #define __xDISABLE_PIC24_USER_INTERRUPT(attrib, ivt, ifsr, ifsb, ipcr, ipcb) BIT_CLEAR(*(&IEC0+ifsr), ifsb)
658 
659 #endif // ESOS_PIC24_IRQ_H
660 
661