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27 #define DISABLE_SCK_PIN 0x1000
28 #define ENABLE_SCK_PIN 0x0000
29 #define SCK_PIN_MASK (~DISABLE_SCK_PIN)
31 #define DISABLE_SDO_PIN 0x0800
32 #define ENABLE_SDO_PIN 0x0000
33 #define SDO_PIN_MASK (~DISABLE_SDO_PIN)
35 #define SPI_MODE16_ON 0x0400
36 #define SPI_MODE8_ON 0x0000
37 #define SPI_MODE_MASK (~SPI_MODE16_ON)
39 #define SPI_SMP_ON 0x0200
40 #define SPI_SMP_OFF 0x0000
41 #define SPI_SMP_MASK (~SPI_SMP_ON)
43 #define SPI_CKE_ON 0x0100
44 #define SPI_CKE_OFF 0x0000
45 #define SPI_CKE_MASK (~SPI_CKE_ON)
47 #define SLAVE_ENABLE_ON 0x0080
48 #define SLAVE_ENABLE_OFF 0x0000
49 #define SLAVE_ENABLE_MASK (~SLAVE_ENABLE_ON)
51 #define CLK_POL_ACTIVE_LOW 0x0040
52 #define CLK_POL_ACTIVE_HIGH 0x0000
53 #define CLK_POL_ACTIVE_MASK (~CLK_POL_ACTIVE_LOW)
55 #define MASTER_ENABLE_ON 0x0020
56 #define MASTER_ENABLE_OFF 0x0000
57 #define MASTER_ENABLE_MASK (~MASTER_ENABLE_ON)
59 #define SEC_PRESCAL_1_1 0x001c
60 #define SEC_PRESCAL_2_1 0x0018
61 #define SEC_PRESCAL_3_1 0x0014
62 #define SEC_PRESCAL_4_1 0x0010
63 #define SEC_PRESCAL_5_1 0x000c
64 #define SEC_PRESCAL_6_1 0x0008
65 #define SEC_PRESCAL_7_1 0x0004
66 #define SEC_PRESCAL_8_1 0x0000
67 #define SEC_PRESCAL_MASK (~SEC_PRESCAL_1_1)
69 #define PRI_PRESCAL_1_1 0x0003
70 #define PRI_PRESCAL_4_1 0x0002
71 #define PRI_PRESCAL_16_1 0x0001
72 #define PRI_PRESCAL_64_1 0x0000
73 #define PRI_PRESCAL_MASK (~PRI_PRESCAL_1_1)
76 #define SPI_ENABLE 0x8000
77 #define SPI_DISABLE 0x0000
78 #define SPI_ENBL_DSBL_MASK (~SPI_ENABLE)
80 #define SPI_IDLE_STOP 0x2000
81 #define SPI_IDLE_CON 0x0000
82 #define SPI_IDLE_MASK (~SPI_IDLE_STOP)
84 #define SPI_RX_OVFLOW 0x0040
85 #define SPI_RX_OVFLOW_CLR 0x0000
88 #define FRAME_ENABLE_ON 0x8000
89 #define FRAME_ENABLE_OFF 0x0000
90 #define FRAME_ENABLE_MASK (~FRAME_ENABLE_ON)
92 #define FRAME_SYNC_INPUT 0x4000
93 #define FRAME_SYNC_OUTPUT 0x0000
94 #define FRAME_SYNC_MASK (~FRAME_SYNC_INPUT)
96 #define FRAME_SYNC_ACTIVE_HIGH 0x2000
97 #define FRAME_SYNC_ACTIVE_LOW 0x0000
98 #define FRAME_SYNC_POL_MASK (~FRAME_SYNC_ACTIVE_HIGH)
100 #define SPI_FRM_PULSE_FIRST_CLK 0x0002
101 #define SPI_FRM_PULSE_PREV_CLK 0x0000
102 #define SPI_FRM_PULSE_MASK (~SPI_FRM_PULSE_FIRST_CLK)
104 #define SPI_ENH_BUFF_ENABLE 0x0001
105 #define SPI_ENH_BUFF_DISABLE 0x0000
106 #define SPI_ENH_BUFF_MASK (~SPI_ENH_BUFF_ENABLE)
109 #if (NUM_SPI_MODS >= 1)
114 #if (NUM_SPI_MODS >= 2)