46 C1CTRL1bits.CANCKS = ECAN_FCAN_IS_FCY;
48 C1CFG2 = ECAN_NO_WAKEUP |
51 ECAN_SEG2_PROGRAMMABLE |
55 C1CFG1 = ECAN_SYNC_JUMP_4 |
59 #warning ECAN module not configured! Edit function configECAN1()
63 #define NUM_TX_BUFS 1 //reserve 1 for TX
64 #define NUM_BUFS 8 //make this a power of 2 for the alignment to work or enter alignment manually
65 ECANMSG msgBuf[NUM_BUFS] __attribute__((space(dma),aligned(NUM_BUFS*16)));
67 #define MSG_ID 0x10B2ABC0 //arbitrary choice for extended messsage ID
70 void configDMA0(
void) {
72 DMA0PAD = (
unsigned int) &C1TXD;
73 DMA0REQ = DMA_IRQ_ECAN1TX;
74 DMA0STA = __builtin_dmaoffset(msgBuf);
75 DMA0CNT =
sizeof(ECANMSG)/2 -1;
79 DMA_DIR_WRITE_PERIPHERAL |
82 DMA_AMODE_PERIPHERAL_INDIRECT |
87 void configDMA1(
void) {
89 DMA1PAD = (
unsigned int) &C1RXD;
90 DMA1REQ = DMA_IRQ_ECAN1RX;
91 DMA1STA = __builtin_dmaoffset(msgBuf);
92 DMA1CNT =
sizeof(ECANMSG)/2 -1;
96 DMA_DIR_READ_PERIPHERAL |
99 DMA_AMODE_PERIPHERAL_INDIRECT |
100 DMA_MODE_CONTINUOUS);
104 #define RX_BUFFER_ID 15 //a value of 15 means to use a FIFO for RX
108 CHANGE_MODE_ECAN1(ECAN_MODE_CONFIGURE);
110 C1FCTRL = ECAN_DMA_BUF_SIZE_8 | ECAN_FIFO_START_AREA_1;
117 for (u8_i = 0; u8_i<8; u8_i++) {
118 if (u8_i < NUM_TX_BUFS)
125 CHANGE_MODE_ECAN1(ECAN_MODE_NORMAL);
131 u32_x = u32_x | 0x8000;
132 }
else u32_x = u32_x >> 1;
137 uint32_t u32_out0, u32_out1, u32_in0, u32_in1;
142 CHANGE_MODE_ECAN1(ECAN_MODE_LOOPBACK);
143 u32_out0 = 0xFEDCBA98;
144 u32_out1 = 0x76543210;
148 msgBuf[0].data.u32[0] = u32_out0;
149 msgBuf[0].data.u32[1] = u32_out1;
159 printf(
"Message ID 0x%lX rejected by acceptance filter.\n",MSG_ID+u8_cnt);
162 rx_buff_id = GET_FIFO_READBUFFER_ECAN1();
163 u32_in0 = msgBuf[rx_buff_id].data.u32[0];
164 u32_in1 = msgBuf[rx_buff_id].data.u32[1];
165 printf(
"Rx Buff: %d. Msg ID: 0x%lX, Out: 0x%lx%lx, In: 0x%lx%lx\n",
169 u32_out0 = rrot32(u32_out0);
170 u32_out1 = rrot32(u32_out1);
172 if (u8_cnt == 8) u8_cnt = 0;