PIC24 Support Libraries
 All Data Structures Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
pic24_configbits.c
Go to the documentation of this file.
1 /*
2  * "Copyright (c) 2008 Robert B. Reese, Bryan A. Jones, J. W. Bruce ("AUTHORS")"
3  * All rights reserved.
4  * (R. Reese, reese_AT_ece.msstate.edu, Mississippi State University)
5  * (B. A. Jones, bjones_AT_ece.msstate.edu, Mississippi State University)
6  * (J. W. Bruce, jwbruce_AT_ece.msstate.edu, Mississippi State University)
7  *
8  * Permission to use, copy, modify, and distribute this software and its
9  * documentation for any purpose, without fee, and without written agreement is
10  * hereby granted, provided that the above copyright notice, the following
11  * two paragraphs and the authors appear in all copies of this software.
12  *
13  * IN NO EVENT SHALL THE "AUTHORS" BE LIABLE TO ANY PARTY FOR
14  * DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT
15  * OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE "AUTHORS"
16  * HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
17  *
18  * THE "AUTHORS" SPECIFICALLY DISCLAIMS ANY WARRANTIES,
19  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
20  * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS
21  * ON AN "AS IS" BASIS, AND THE "AUTHORS" HAS NO OBLIGATION TO
22  * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
23  *
24  * Please maintain this header in its entirety when copying/modifying
25  * these files.
26  *
27  *
28  */
29 
30 
31 // Documentation for this file. If the \file tag isn't present,
32 // this file won't be documented.
33 /** \file
34  * This file contains configuration bit settings. Important points on the
35  * syntax used:
36  * - The "functions" below are actually macros which set
37  * these configuration bits. For more details, see
38  * the chip-specific include file, such as <code>p24HJ12GP201.h</code>
39  * in <code>C:\\Program Files\\Microchip\\MPLAB C30\\support\\h</code>,
40  * <!-- Note: extra \\ needed to prevent Doxygen errors, but
41  * these are not actually part of the path.
42  * --> which contain macros (starting on line 2843) to ease setting
43  * configuration bits.
44  * - Instead of ORing bits, AND them: use for example
45  * <code>GSS_OFF & GCP_OFF</code>, NOT
46  * <code>GSS_OFF | GCP_OFF</code>.
47  * - Only one invocation of each config register
48  * should appear in a project, at the top of a C
49  * source file (outside of any function).
50  * - All possible configuration options are listed; the
51  * option currently in use is indicated by an arrow
52  * <code>--></code> next to the setting.
53  * - This file contains configuration settings for some of the
54  * PIC24 family of chips. To change or add support for a new
55  * chip, examine the include-file documentation and read the
56  * FRM documentation on config bits plus the chip-specific
57  * documentation on config bits.
58  *
59  * Note on clock choice: The processor is configured to always
60  * start up with the FRC, rather than what it will use after
61  * clock configuration. This guarantees a working clock at
62  * power-up, which can then be changed by the bootloader / user
63  * code / etc.
64  */
65 
66 #include "pic24_clockfreq.h"
67 
68 /// \name PIC24H configuration bits
69 //@{
70 #if (defined(__PIC24HJ12GP202__) || \
71 defined(__PIC24HJ12GP201__) || \
72 defined(__PIC24HJ32GP202__) || \
73 defined(__PIC24HJ32GP202__) || \
74 defined(__PIC24HJ16GP304__) || \
75 defined(__DOXYGEN__)) // NOTE: DOXYGEN only used for documentation generation
76 
77 
78 /** FBS: Boot Code Segment Configuration Register
79  ** \code
80  ** Boot Segment Program Memory:
81  ** BSS_HIGH_LARGE_BOOT_CODE High Security Lar Boot Flash
82  ** BSS_LARGE_FLASH_HIGH High Security Lar Boot Flash
83  ** BSS_HIGH_MEDIUM_BOOT_CODE High Security Med Boot Flash
84  ** BSS_MEDIUM_FLASH_HIGH High Security Med Boot Flash
85  ** BSS_HIGH_SMALL_BOOT_CODE High Security Small Boot Flash
86  ** BSS_SMALL_FLASH_HIGH High Security Small Boot Flash
87  ** BSS_LARGE_FLASH_STD Standard Security Lar Boot Flash
88  ** BSS_STRD_LARGE_BOOT_CODE Standard Security Lar Boot Flash
89  ** BSS_MEDIUM_FLASH_STD Standard Security Med Boot Flash
90  ** BSS_STRD_MEDIUM_BOOT_CODE Standard Security Med Boot Flash
91  ** BSS_SMALL_FLASH_STD Standard Security Small Boot Flash
92  ** BSS_STRD_SMALL_BOOT_CODE Standard Security Small Boot Flash
93  ** BSS_NO_BOOT_CODE No Boot Segment Program Memory
94  ** BSS_NO_FLASH No Boot Segment Program Memory
95  **
96  ** Write Protect :
97  ** BWRP_WRPROTECT_ON Enabled
98  ** -->BWRP_WRPROTECT_OFF Disabled
99  ** Note: since this is off, size bits above don't matter.
100  \endcode
101  */
102 _FBS(BWRP_WRPROTECT_OFF);
103 
104 /* FSS: Secure Code Segment Configuration Register
105 ** Not present on this chip.
106 */
107 
108 /** FGS: General Code Segment Configuration Register
109  ** \code
110  ** Code Protect:
111  ** GSS_HIGH high security protect on
112  ** GSS_STD standard security code protect on
113  ** -->GSS_OFF code protect off
114  **
115  ** Code Protect:
116  ** GCP_ON Enabled
117  ** -->GCP_OFF Disabled
118  ** These bits aren't mentioned in the manuals!
119  ** Probably a typo in the .h file.
120  **
121  ** Write Protect:
122  ** GWRP_ON Enabled
123  ** -->GWRP_OFF Disabled
124  **
125  \endcode
126  */
127 _FGS(GSS_OFF & GCP_OFF & GWRP_OFF);
128 
129 
130 /** FOSCSEL: Oscillator Source Selection Register
131  ** \code
132  ** Oscillator Source Selection:
133  ** -->FNOSC_FRC Fast RC oscillator
134  ** FNOSC_FRCPLL Fast RC oscillator w/ divide and PLL
135  ** FNOSC_PRI Primary oscillator (XT, HS, EC)
136  ** FNOSC_PRIPLL Primary oscillator (XT, HS, EC) w/ PLL
137  ** FNOSC_SOSC Secondary oscillator
138  ** FNOSC_LPRC Low power RC oscillator
139  ** FNOSC_FRCDIV16 Fast RC oscillator w/ divide by 16
140  ** FNOSC_LPRCDIVN Low power Fast RC oscillator w/divide by N
141  **
142  ** Two-speed Oscillator Startup :
143  ** IESO_ON Enabled
144  ** -->IESO_OFF Disabled
145  **
146  \endcode
147  */
148 _FOSCSEL(FNOSC_FRC & IESO_OFF);
149 
150 /** FOSC: Oscillator Configuration Register
151  ** \code
152  ** Clock switching and clock monitor:
153  ** FCKSM_CSECME Both enabled
154  ** -->FCKSM_CSECMD Only clock switching enabled
155  ** FCKSM_CSDCMD Both disabled
156  ** Clock switching must be enabled to allow a switch
157  ** up to the PLL.
158  **
159  ** Single configuration for remappable I/O:
160  ** -->IOL1WAY_OFF Disabled
161  ** IOL1WAY_ON Enabled
162  **
163  ** OSC2 Pin function:
164  ** -->OSCIOFNC_ON Digital I/O
165  ** OSCIOFNC_OFF OSC2 is clock O/P
166  ** Note: this frees up OSC1 for digitial I/O when
167  ** not in HS or XT modes (per POSCMD_SEL).
168  **
169  ** Oscillator Selection:
170  ** Taken from POSCMD_SEL
171  **
172  \endcode
173  */
174 _FOSC(FCKSM_CSECMD & IOL1WAY_OFF & OSCIOFNC_ON & POSCMD_SEL);
175 
176 
177 /** FWDT: Watchdog Timer Configuration Register
178  ** \code
179  ** Watchdog Timer:
180  ** -->FWDTEN_OFF Disabled
181  ** FWDTEN_ON Enabled
182  **
183  ** Windowed WDT:
184  ** WINDIS_ON Enabled
185  ** -->WINDIS_OFF Disabled
186  **
187  ** Watchdog prescaler:
188  ** WDTPRE_PR32 1:32
189  ** -->WDTPRE_PR128 1:128
190  **
191  ** Watchdog postscaler:
192  ** WDTPOST_PS1 1:1
193  ** WDTPOST_PS2 1:2
194  ** WDTPOST_PS4 1:4
195  ** WDTPOST_PS8 1:8
196  ** WDTPOST_PS16 1:16
197  ** WDTPOST_PS32 1:32
198  ** WDTPOST_PS64 1:64
199  ** WDTPOST_PS128 1:128
200  ** WDTPOST_PS256 1:256
201  ** -->WDTPOST_PS512 1:512
202  ** WDTPOST_PS1024 1:1,024
203  ** WDTPOST_PS2048 1:2,048
204  ** WDTPOST_PS4096 1:4,096
205  ** WDTPOST_PS8192 1:8,192
206  ** WDTPOST_PS16384 1:16,384
207  ** WDTPOST_PS32768 1:32,768
208  ** 128*512 = 65536 ~ 0.5 Hz ~ 2 secs (WDT is ~ 32 KHz)
209  \endcode
210  */
211 _FWDT(FWDTEN_OFF & WINDIS_OFF & WDTPRE_PR128 & WDTPOST_PS512);
212 
213 /** FPOR: POR Configuration Register
214  ** \code
215  ** Power-on Reset Value:
216  ** FPWRT_PWR1 Disabled
217  ** FPWRT_PWR2 2ms
218  ** FPWRT_PWR4 4ms
219  ** FPWRT_PWR8 8ms
220  ** -->FPWRT_PWR16 16ms
221  ** FPWRT_PWR32 32ms
222  ** FPWRT_PWR64 64ms
223  ** FPWRT_PWR128 128ms
224  **
225  ** Aletrnate I2C Pins:
226  ** ALTI2C_ON I2C mapped to ASDA1/ASCL1
227  ** -->ALTI2C_OFF I2C mapped to SDA1/SCL1
228  **
229  \endcode
230  */
231 _FPOR(FPWRT_PWR16 & ALTI2C_OFF);
232 
233 /** FICD: the debugger configuration word.
234  ** \code
235  ** JTAG Enable Bit:
236  ** -->JTAGEN_OFF JTAG is disabled
237  ** JTAGEN_ON JTAG is enabled
238  ** The one important thing in this
239  ** field for normal use is to disable the JTAG mode. If you do not
240  ** disable the JTAG mode, then the TDI, TMS, TDO, TCK pins are
241  ** not usable which severly limits the GP202/GP201 processors.
242  **
243  ** ICD communication channel select bits:
244  ** ICS_NONE Reserved
245  ** ICS_PGD3 communicate on PGC3/EMUC3 and PGD3/EMUD3
246  ** ICS_PGD2 communicate on PGC2/EMUC2 and PGD2/EMUD2
247  ** -->ICS_PGD1 communicate on PGC1/EMUC1 and PGD1/EMUD1
248  **
249  \endcode
250  */
251 _FICD(JTAGEN_OFF & ICS_PGD1);
252 
253 ///\cond doxygen_ignore
254 #define CONFIG_BITS_DEFINED
255 ///\endcond
256 
257 #endif // #ifdef (lots of PIC24H devices)
258 //@}
259 
260 
261 #if defined(EXPLORER16_100P) && defined(__PIC24HJ256GP610__)
262 _FBS(BWRP_WRPROTECT_OFF);
263 _FGS(GSS_OFF & GCP_OFF & GWRP_OFF);
264 _FOSCSEL(FNOSC_FRC & IESO_OFF);
265 _FOSC(FCKSM_CSECMD & OSCIOFNC_OFF & POSCMD_SEL);
266 _FWDT(FWDTEN_OFF & WINDIS_OFF & WDTPRE_PR128 & WDTPOST_PS512);
267 _FPOR(FPWRT_PWR16);
268 _FICD(JTAGEN_OFF & ICS_PGD1);
269 #define CONFIG_BITS_DEFINED
270 #endif
271 
272 
273 /// \name PIC24F configuration bits
274 //@{
275 #if (defined(__PIC24FJ64GA002__) ) || defined(__DOXYGEN__)
276 
277 /** Register CONFIG1
278  ** \code
279  ** JTAG:
280  ** -->JTAGEN_OFF Disabled
281  ** JTAGEN_ON Enabled
282  **
283  ** Code Protect:
284  ** GCP_ON Enabled
285  ** -->GCP_OFF Disabled
286  **
287  ** Write Protect:
288  ** GWRP_ON Enabled
289  ** -->GWRP_OFF Disabled
290  **
291  ** Background Debugger:
292  ** BKBUG_ON Enabled
293  ** -->BKBUG_OFF Disabled
294  **
295  ** Clip-on Emulation mode:
296  ** COE_ON Enabled
297  ** -->COE_OFF Disabled
298  **
299  ** ICD pins select:
300  ** ICS_PGx3 EMUC/EMUD share PGC3/PGD3
301  ** ICS_PGx2 EMUC/EMUD share PGC2/PGD2
302  ** -->ICS_PGx1 EMUC/EMUD share PGC1/PGD1
303  **
304  ** Watchdog Timer:
305  ** -->FWDTEN_OFF Disabled
306  ** FWDTEN_ON Enabled
307  **
308  ** Windowed WDT:
309  ** WINDIS_ON Enabled
310  ** -->WINDIS_OFF Disabled
311  **
312  ** Watchdog prescaler:
313  ** FWPSA_PR32 1:32
314  ** -->FWPSA_PR128 1:128
315  **
316  ** Watchdog postscale:
317  ** WDTPS_PS1 1:1
318  ** WDTPS_PS2 1:2
319  ** WDTPS_PS4 1:4
320  ** WDTPS_PS8 1:8
321  ** WDTPS_PS16 1:16
322  ** WDTPS_PS32 1:32
323  ** WDTPS_PS64 1:64
324  ** WDTPS_PS128 1:128
325  ** WDTPS_PS256 1:256
326  ** -->WDTPS_PS512 1:512
327  ** WDTPS_PS1024 1:1,024
328  ** WDTPS_PS2048 1:2,048
329  ** WDTPS_PS4096 1:4,096
330  ** WDTPS_PS8192 1:8,192
331  ** WDTPS_PS16384 1:16,384
332  ** WDTPS_PS32768 1:32,768
333  ** 128*512 = 65536 ~ 0.5 Hz ~ 2 secs (WDT is ~ 31 KHz)
334  \endcode
335  */
336 _CONFIG1(JTAGEN_OFF & GCP_OFF & GWRP_OFF & BKBUG_OFF & COE_OFF & ICS_PGx1 & FWDTEN_OFF & WINDIS_OFF & FWPSA_PR128 & WDTPS_PS512);
337 
338 
339 /** Register CONFIG2
340  ** \code
341  ** Two Speed Start-up:
342  ** -->IESO_OFF Disabled
343  ** IESO_ON Enabled
344  **
345  ** Secondary Oscillator:
346  ** SOSCSEL_LPSOSC Low Power Secondary Oscillator
347  ** SOSCSEL_SOSC Default Secondary Oscillator
348  **
349  ** Voltage Regulator Standby-mode Wake-up Timer:
350  ** WUTSEL_FST Fast Wake-up timer selected
351  ** WUTSEL_LEG Legacy Wake-up timer selected
352  **
353  ** Oscillator Selection:
354  ** -->FNOSC_FRC Fast RC oscillator
355  ** FNOSC_FRCPLL Fast RC oscillator w/ divide and PLL
356  ** FNOSC_PRI Primary oscillator (XT, HS, EC)
357  ** FNOSC_PRIPLL Primary oscillator (XT, HS, EC) w/ PLL
358  ** FNOSC_SOSC Secondary oscillator
359  ** FNOSC_LPRC Low power RC oscillator
360  ** FNOSC_FRCDIV Fast RC oscillator with divide
361  **
362  ** Clock switching and clock monitor:
363  ** FCKSM_CSECME Both enabled
364  ** -->FCKSM_CSECMD Only clock switching enabled
365  ** FCKSM_CSDCMD Both disabled
366  **
367  ** OSCO/RC15 function:
368  ** -->OSCIOFNC_ON RC15
369  ** OSCIOFNC_OFF OSCO or Fosc/2
370  **
371  ** RP Register Protection:
372  ** -->IOL1WAY_OFF Unlimited Writes To RP Registers
373  ** IOL1WAY_ON Write RP Registers Once
374  **
375  ** I2C1 pins Select:
376  ** I2C1SEL_SEC Use Secondary I2C1 pins
377  ** -->I2C1SEL_PRI Use Primary I2C1 pins
378  **
379  ** Oscillator Selection:
380  ** Taken from POSCMD_SEL
381  **
382 \endcode
383 */
384 _CONFIG2(IESO_OFF & FNOSC_FRC & FCKSM_CSECMD & OSCIOFNC_ON & IOL1WAY_OFF & POSCMD_SEL);
385 
386 
387 ///\cond doxygen_ignore
388 #define CONFIG_BITS_DEFINED
389 ///\endcond
390 //@}
391 #endif // #ifdef PIC24F processors
392 
393 #if defined(EXPLORER16_100P) && defined(__PIC24FJ128GA010__)
394 _CONFIG1(JTAGEN_OFF & GCP_OFF & GWRP_OFF & BKBUG_OFF & COE_OFF & ICS_PGx1 & FWDTEN_OFF & WINDIS_OFF & FWPSA_PR128 & WDTPS_PS512);
395 _CONFIG2(IESO_OFF & FNOSC_FRC & FCKSM_CSECMD & OSCIOFNC_OFF & POSCMD_SEL);
396 #define CONFIG_BITS_DEFINED
397 #endif
398 
399 #if defined(__PIC24FJ64GB002__) ||(__PIC24FJ64GB004__)
400 _CONFIG1(JTAGEN_OFF & GCP_OFF & GWRP_OFF & ICS_PGx1 & FWDTEN_OFF & WINDIS_OFF & FWPSA_PR128 & WDTPS_PS512);
401 _CONFIG2(IESO_OFF & FNOSC_FRC & FCKSM_CSECMD & OSCIOFNC_ON & IOL1WAY_OFF & POSCMD_SEL & PLL96MHZ_OFF & PLLDIV_DIV2 );
402 _CONFIG4(DSWDTPS_DSWDTPSF & DSWDTEN_OFF & DSBOREN_OFF)
403 #define CONFIG_BITS_DEFINED
404 ///\endcond
405 #endif
406 
407 //default config bits, use these if a processor is not defined.
408 #ifndef CONFIG_BITS_DEFINED
409 #ifdef __PIC24H__
410 _FBS(BWRP_WRPROTECT_OFF);
411 _FGS(GSS_OFF & GCP_OFF & GWRP_OFF);
412 
413 #ifdef RSS_NO_RAM
414 _FSS(RSS_NO_RAM & SSS_NO_FLASH & SWRP_WRPROTECT_OFF);
415 #endif
416 
417 #ifdef IOL1WAY_OFF
418 _FOSC(FCKSM_CSECMD & IOL1WAY_OFF & OSCIOFNC_ON & POSCMD_SEL);
419 #else
420 _FOSC(FCKSM_CSECMD & OSCIOFNC_ON & POSCMD_SEL);
421 #endif
422 _FOSCSEL(FNOSC_FRC & IESO_OFF);
423 _FWDT(FWDTEN_OFF & WINDIS_OFF & WDTPRE_PR128 & WDTPOST_PS512);
424 _FPOR(FPWRT_PWR16);
425 _FICD(JTAGEN_OFF & ICS_PGD1);
426 
427 #warning Using default config bit settings for the PIC24H family.
428 #warning Edit this file to define bits for your processor!
429 ///\cond doxygen_ignore
430 #define CONFIG_BITS_DEFINED
431 ///\endcond
432 #endif
433 
434 #ifdef __PIC24F__
435 
436 #ifndef BKBUG_OFF
437 #define BKBUG_OFF 0xFFFF
438 #endif
439 #ifndef COE_OFF
440 #define COE_OFF 0xFFFF
441 #endif
442 
443 _CONFIG1(JTAGEN_OFF & GCP_OFF & GWRP_OFF & BKBUG_OFF & COE_OFF & ICS_PGx1 & FWDTEN_OFF & WINDIS_OFF & FWPSA_PR128 & WDTPS_PS512);
444 
445 #ifndef IOL1WAY_OFF
446 #define IOL1WAY_OFF 0xFFFF
447 #endif
448 _CONFIG2(IESO_OFF & FNOSC_FRC & FCKSM_CSECMD & OSCIOFNC_ON & IOL1WAY_OFF & POSCMD_SEL);
449 
450 #warning Using default config bit settings for the PIC24F family.
451 #warning Edit this file to define bits for your processor!
452 ///\cond doxygen_ignore
453 #define CONFIG_BITS_DEFINED
454 ///\endcond
455 #endif
456 
457 
458 
459 /* The PIC24FK is a subfamily of the PIC24F -- functionality like the PIC24F, but config bits like the PIC24H */
460 #ifdef __PIC24FK__
461 _FBS(BSS_OFF & BWRP_OFF);
462 _FGS(GCP_OFF & GWRP_OFF);
463 
464 #if (POSC_FREQ < 100000L)
465 _FOSC(FCKSM_CSECMD & OSCIOFNC_ON & POSCMD_SEL & POSCFREQ_LS);
466 #elif (POSC_FREQ > 8000000L)
467 _FOSC(FCKSM_CSECMD & OSCIOFNC_ON & POSCMD_SEL & POSCFREQ_HS);
468 #else
469 _FOSC(FCKSM_CSECMD & OSCIOFNC_ON & POSCMD_SEL & POSCFREQ_MS);
470 #endif
471 
472 
473 _FOSCSEL(FNOSC_FRC & IESO_OFF);
474 _FWDT(FWDTEN_OFF & WINDIS_OFF & FWPSA_PR128 & WDTPS_PS512);
475 _FPOR(PWRTEN_ON & MCLRE_ON & I2C1SEL_PRI);
476 _FICD(BKBUG_OFF & ICS_PGx1);
477 
478 //new config word for deep sleep operation, set these for your needs
479 _FDS(DSWDTEN_OFF & DSBOREN_OFF & RTCOSC_LPRC & DSWDTOSC_SOSC);
480 
481 #warning Using default config bit settings for the PIC24FK family.
482 #warning Edit this file to define bits for your processor!
483 ///\cond doxygen_ignore
484 #define CONFIG_BITS_DEFINED
485 ///\endcond
486 #endif
487 
488 
489 #ifdef __dsPIC33F__
490 _FBS(BWRP_WRPROTECT_OFF);
491 _FGS(GSS_OFF & GCP_OFF & GWRP_OFF);
492 _FOSCSEL(FNOSC_FRC & IESO_OFF);
493 #ifdef RSS_NO_RAM
494 _FSS(RSS_NO_RAM & SSS_NO_FLASH & SWRP_WRPROTECT_OFF);
495 #endif
496 #ifdef IOL1WAY_OFF
497 _FOSC(FCKSM_CSECMD & IOL1WAY_OFF & OSCIOFNC_ON & POSCMD_SEL);
498 #else
499 _FOSC(FCKSM_CSECMD & OSCIOFNC_ON & POSCMD_SEL);
500 #endif
501 _FWDT(FWDTEN_OFF & WINDIS_OFF & WDTPRE_PR128 & WDTPOST_PS512);
502 _FPOR(FPWRT_PWR16);
503 _FICD(JTAGEN_OFF & ICS_PGD1 & 0xFFEF);
504 #warning Using default config bit settings for the dsPIC33F family.
505 #warning Edit this file to define bits for your processor!
506 ///\cond doxygen_ignore
507 #define CONFIG_BITS_DEFINED
508 ///\endcond
509 #endif
510 
511 #ifdef __PIC24E__
512 #ifdef GCP_OFF
513 _FGS( GCP_OFF & GWRP_OFF);
514 #else
515 _FGS(0xFFFF);
516 #endif
517 //28 pin devices only have ALT2IC1 pins!!?
518 _FPOR(ALTI2C1_ON & 0xFFFF);
519 
520 #ifdef IOL1WAY_OFF
521 _FOSC(FCKSM_CSECMD & IOL1WAY_OFF & OSCIOFNC_ON & POSCMD_SEL);
522 //_FOSC(FCKSM_CSECMD & IOL1WAY_OFF & OSCIOFNC_OFF & POSCMD_SEL);
523 #else
524 _FOSC(FCKSM_CSECMD & OSCIOFNC_ON & POSCMD_SEL);
525 #endif
526 _FOSCSEL(FNOSC_FRC & IESO_OFF);
527 _FWDT(FWDTEN_OFF & WINDIS_OFF & WDTPRE_PR128 & WDTPOST_PS512);
528 _FICD(JTAGEN_OFF & ICS_PGD1 & 0xFFEF);
529 
530 #warning Using default config bit settings for the PIC24E family.
531 #warning Edit this file to define bits for your processor!
532 ///\cond doxygen_ignore
533 #define CONFIG_BITS_DEFINED
534 ///\endcond
535 #endif
536 
537 
538 #ifdef __dsPIC33E__
539 #ifdef GCP_OFF
540 _FGS( GCP_OFF & GWRP_OFF);
541 #else
542 _FGS(0xFFFF);
543 #endif
544 
545 //28 pin devices only have ALT2IC1 pins!!?
546 _FPOR(ALTI2C1_ON & 0xFFFF);
547 
548 #ifdef IOL1WAY_OFF
549 _FOSC(FCKSM_CSECMD & IOL1WAY_OFF & OSCIOFNC_ON & POSCMD_SEL);
550 //_FOSC(FCKSM_CSECMD & IOL1WAY_OFF & OSCIOFNC_OFF & POSCMD_SEL);
551 #else
552 _FOSC(FCKSM_CSECMD & OSCIOFNC_ON & POSCMD_SEL);
553 #endif
554 _FOSCSEL(FNOSC_FRC & IESO_OFF);
555 _FWDT(FWDTEN_OFF & WINDIS_OFF & WDTPRE_PR128 & WDTPOST_PS512);
556 _FICD(JTAGEN_OFF & ICS_PGD1 & 0xFFEF);
557 
558 #warning Using default config bit settings for the dsPIC33E family.
559 #warning Edit this file to define bits for your processor!
560 ///\cond doxygen_ignore
561 #define CONFIG_BITS_DEFINED
562 ///\endcond
563 #endif
564 
565 
566 #endif
567 
568 
569 #ifndef CONFIG_BITS_DEFINED
570 #error Edit 'common/pic24_configbits.c' to add config bits for your processor!
571 #endif
572 
573 
574 
575