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44 #ifndef ESOS_PIC24_IRQ_H
45 #define ESOS_PIC24_IRQ_H
75 #define ESOS_USER_INTERRUPT(desc) __xESOS_USER_ISR(desc)
76 #define __xESOS_USER_ISR(attrib, ivt, ifsr, ifsb, ipcr, ipcb) void _ISRFAST attrib (void)
93 #define ESOS_USER_IRQ_LEVEL1 6
99 #define ESOS_USER_IRQ_LEVEL2 4
105 #define ESOS_USER_IRQ_LEVEL3 3
111 #define ESOS_USER_IRQ_LEVEL4 2
113 #define __ESOS_USER_IRQ_UNREGISTERED 0
115 #define __ESOS_DISABLE_USER_IRQS_LEVEL ESOS_USER_IRQ_LEVEL2
117 #define __ESOS_ENABLE_USER_IRQS_LEVEL __ESOS_USER_IRQ_UNREGISTERED
122 #if defined(__PIC24HJ32GP202__) || defined(__DOXYGEN__)
138 #define ESOS_IRQ_PIC24_AD1 _ADC1Interrupt, 0x002E, 0, 13, 3, 4 // AD1 Conversion complete
153 #define ESOS_IRQ_PIC24_SPI1 _SPI1Interrupt, 0x0028, 0, 10, 2, 8 // SPI1 event
168 #define ESOS_IRQ_PIC24_SPI1E _SPI1ErrInterrupt, 0x0026, 0, 9, 2, 4 // SPI1 (exception) fault event
183 #define ESOS_IRQ_PIC24_T3 _T3Interrupt, 0x0024, 0, 8, 2, 0 // Timer 3
198 #define ESOS_IRQ_PIC24_T2 _T2Interrupt, 0x0022, 0, 7, 1, 12 // Timer 2
213 #define ESOS_IRQ_PIC24_OC2 _OC2Interrupt, 0x0020, 0, 6, 1, 8 // Output compare channel 2
228 #define ESOS_IRQ_PIC24_IC2 _IC2Interrupt, 0x001E, 0, 5, 1, 4 // Input capture channel 2
243 #define ESOS_IRQ_PIC24_OC1 _OC1Interrupt, 0x0018, 0, 2, 0, 8 // Output compare channel 1
259 #define ESOS_IRQ_PIC24_IC1 _IC1Interrupt, 0x0016, 0, 1, 0, 4 // Input capture channel 1
274 #define ESOS_IRQ_PIC24_INT0 _INT0Interrupt, 0x0014, 0, 0, 0, 0 // external interrupt 0
289 #define ESOS_IRQ_PIC24_INT2 _INT2Interrupt, 0x004E, 1, 13, 7, 4 // external interrupt 2
305 #define ESOS_IRQ_PIC24_IC8 _IC8Interrupt, 0x0042, 1, 7, 5, 12 // Input capture channel 8
320 #define ESOS_IRQ_PIC24_IC7 _IC7Interrupt, 0x0040, 1, 6, 5, 8 // Input capture channel 7
335 #define ESOS_IRQ_PIC24_INT1 _INT1Interrupt, 0x003C, 1, 4, 5, 0 // external interrupt 1
350 #define ESOS_IRQ_PIC24_CN _CNInterrupt, 0x003A, 1, 3, 4, 12 // input change notification
365 #define ESOS_IRQ_PIC24_MI2C1 _MI2C1Interrupt, 0x0036, 1, 1, 4, 4 // I2C1 Master event
380 #define ESOS_IRQ_PIC24_SI2C1 _SI2C1Interrupt, 0x0034, 1, 0, 4, 0 // I2C1 slave event
385 #if !defined(_ESOS_PIC24_RS232_H) || defined(__DOXYGEN__)
401 #define ESOS_IRQ_PIC24_U1TX _U1TXInterrupt, 0x002C, 0, 12, 3, 0 // UART1 TX event
417 #define ESOS_IRQ_PIC24_U1RX _U1RXInterrupt, 0x002A, 0, 11, 2, 12 // UART1 RX event
434 #define ESOS_IRQ_PIC24_U1E _U1ErrInterrupt, 0x0096, 4, 1, 16, 4 // UART1 Error event
436 #endif // end of UART1 constants
438 #endif // __PIC24HJ32GP202__
444 #define __GET_IRQ_ATTRIB(Q) __xGET_IRQ_ATTRIB(Q)
445 #define __GET_IVTQ(Q) __xGET_IVT(Q)
446 #define __GET_IFS_NUM(Q) __xGET_IFS_NUM(Q)
447 #define __GET_IFS_BITNUM(Q) __xGET_IFS_BITNUM(Q)
448 #define __GET_IEC_NUM(Q) __xGET_IFS_NUM(Q)
449 #define __GET_IEC_BITNUM(Q) __xGET_IFS_BITNUM(Q)
450 #define __GET_IPC_NUM(Q) __xGET_IPC_NUM(Q)
451 #define __GET_IPC_BITNUM(Q) __xGET_IPC_BITNUM(Q)
453 #define __xGET_IRQ_ATTRIB(attrib, ivt, ifsr, ifsb, ipcr, ipcb) attrib
454 #define __xGET_IVT(attrib, ivt, ifsr, ifsb, ipcr, ipcb) ivt
455 #define __xGET_IFS_NUM(attrib, ivt, ifsr, ifsb, ipcr, ipcb) ifsr
456 #define __xGET_IFS_BITNUM(attrib, ivt, ifsr, ifsb, ipcr, ipcb) ifsb
457 #define __xGET_IEC_NUM(attrib, ivt, ifsr, ifsb, ipcr, ipcb) ifsr
458 #define __xGET_IEC_BITNUM(attrib, ivt, ifsr, ifsb, ipcr, ipcb) ifsb
459 #define __xGET_IPC_NUM(attrib, ivt, ifsr, ifsb, ipcr, ipcb) ipcr
460 #define __xGET_IPC_BITNUM(attrib, ivt, ifsr, ifsb, ipcr, ipcb) ipcb
464 #define __GET_IPL_FROM_IPCX(Q) ((*(&IPC0+(__xGET_IPC_NUM(Q))) >> __xGET_IPC_BITNUM(Q))&0x7)
468 #define __IS_IPL_FROM_IPCX(Q, val) ((__GET_IPL_FROM_IPCX(Q))==(val))
471 #define __PUT_IPL_INTO_IPCX(ipc,ipcb,ipl) \
473 BIT_CLEAR_MASK( *(&IPC0+(ipc)), 0x07<<ipcb) + (ipl<<ipcb); \
474 *(&IPC0+ipc) += (ipl<<ipcb); \
493 #define ESOS_UNREGISTER_PIC24_USER_INTERRUPT(desc) __xUNREGISTER_PIC24_USER_INTERRUPT(desc)
494 #define __xUNREGISTER_PIC24_USER_INTERRUPT(attrib, ivt, ifsr, ifsb, ipcr, ipcb) \
496 __xDISABLE_PIC24_USER_INTERRUPT(attrib, ivt, ifsr, ifsb, ipcr, ipcb); \
497 __PUT_IPL_INTO_IPCX(ipcr,ipcb, __ESOS_USER_IRQ_UNREGISTERED); \
520 #define ESOS_REGISTER_PIC24_USER_INTERRUPT(desc, ipl, p2f) __xREGISTER_PIC24_USER_INTERRUPT(desc, ipl, p2f)
521 #define __xREGISTER_PIC24_USER_INTERRUPT(attrib, ivt, ifsr, ifsb, ipcr, ipcb, ipl, p2f) \
523 __xDISABLE_PIC24_USER_INTERRUPT(attrib, ivt, ifsr, ifsb, ipcr, ipcb); \
524 __PUT_IPL_INTO_IPCX(ipcr, ipcb, ipl); \
542 #define ESOS_DISABLE_ALL_PIC24_USER_INTERRUPTS() SET_CPU_IPL(__ESOS_DISABLE_USER_IRQS_LEVEL)
558 #define ESOS_ENABLE_ALL_PIC24_USER_INTERRUPTS() SET_CPU_IPL(__ESOS_ENABLE_USER_IRQS_LEVEL)
578 #define ESOS_IS_PIC24_USER_INTERRUPT_ENABLED(desc) __xIS_PIC24_USER_INTERRUPT_ENABLED(desc)
579 #define __xIS_PIC24_USER_INTERRUPT_ENABLED(attrib, ivt, ifsr, ifsb, ipcr, ipcb) IS_BIT_SET(*(&IEC0+ifsr),ifsb)
599 #define ESOS_DOES_PIC24_USER_INTERRUPT_NEED_SERVICING(desc) __xDOES_PIC24_USER_INTERRUPT_NEED_SERVICING(desc)
600 #define __xDOES_PIC24_USER_INTERRUPT_NEED_SERVICING(attrib, ivt, ifsr, ifsb, ipcr, ipcb) IS_BIT_SET(*(&IFS0+ifsr), ifsb)
618 #define ESOS_MARK_PIC24_USER_INTERRUPT_SERVICED(desc) __xMARK_PIC24_USER_INTERRUPT_SERVICED(desc)
619 #define __xMARK_PIC24_USER_INTERRUPT_SERVICED(attrib, ivt, ifsr, ifsb, ipcr, ipcb) BIT_CLEAR(*(&IFS0+ifsr),ifsb)
637 #define ESOS_ENABLE_PIC24_USER_INTERRUPT(desc) __xENABLE_PIC24_USER_INTERRUPT(desc)
638 #define __xENABLE_PIC24_USER_INTERRUPT(attrib, ivt, ifsr, ifsb, ipcr, ipcb) BIT_SET(*(&IEC0+ifsr), ifsb)
656 #define ESOS_DISABLE_PIC24_USER_INTERRUPT(desc) __xDISABLE_PIC24_USER_INTERRUPT(desc)
657 #define __xDISABLE_PIC24_USER_INTERRUPT(attrib, ivt, ifsr, ifsb, ipcr, ipcb) BIT_CLEAR(*(&IEC0+ifsr), ifsb)
659 #endif // ESOS_PIC24_IRQ_H