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pic24_timer.h
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1 /* Standard copyright does not go in this file because
2 * of the use of Microchip provided macros, see comments below.
3 */
4 // Documentation for this file. If the \file tag isn't present,
5 // this file won't be documented.
6 /** \file
7  * To do.
8  */
9 
10 #ifndef _PIC24_TIMER_H_
11 #define _PIC24_TIMER_H_
12 
13 #include <stdint.h>
14 #include "pic24_chip.h"
15 #include "pic24_clockfreq.h"
16 
17 /** Given the TxCON register as a bitfield, determines the prescale
18  * based on the TCKPS bitfield. Works for PIC24H, PIC24F timers.
19  * Simply accesses the TCKPS bitfield then calls
20  * \ref getTimerPrescaleBits with the bitfield.
21  * \param TxCONbits The TxCONbits for the timer in question
22  * \return Prescale value.
23  */
24 #define getTimerPrescale(TxCONbits) getTimerPrescaleBits(TxCONbits.TCKPS)
25 
26 #define MS_TO_TICKS(ms, pre) ((FCY/1000L/(pre))*ms)
27 uint16_t msToU16Ticks(uint16_t u16_ms, uint16_t u16_pre);
28 uint16_t usToU16Ticks(uint16_t u16_us, uint16_t u16_pre);
29 uint32_t usToU32Ticks(uint32_t u32_us, uint16_t u16_pre);
31 uint32_t ticksToMs (uint32_t u32_ticks, uint16_t u16_tmrPre);
32 uint32_t ticksToUs (uint32_t u32_ticks, uint16_t u16_tmrPre);
33 uint32_t ticksToNs (uint32_t u32_ticks, uint16_t u16_tmrPre);
34 uint32_t computeDeltaTicksLong(uint16_t u16_start, uint16_t u16_end, uint16_t u16_tmrPR, uint16_t u16_oflows);
35 uint16_t computeDeltaTicks(uint16_t u16_start, uint16_t u16_end, uint16_t u16_tmrPR);
36 
37 /*
38 The following macros are a subset of the AND/OR macros found in the
39 the MPLAB C30/src/peripheral_24F/timer.h file and placed
40 in this header for use solely and exclusively on Microchip
41 PICmicro Microcontroller products as
42 specified in the MPLAB C30/src/peripheral_24F/timer.h header.
43 
44 Edits have been made in the comments to correct some
45 minor typos.
46 */
47 
48 /* T1CON: TIMER1 CONTROL REGISTER */
49 #define T1_ON 0x8000 /* Timer1 ON */
50 #define T1_OFF 0x0000 /* Timer1 OFF */
51 #define T1_OFF_ON_MASK (~T1_ON)
52 
53 #define T1_IDLE_STOP 0x2000 /* stop operation during sleep */
54 #define T1_IDLE_CON 0x0000 /* operate during sleep */
55 #define T1_IDLE_MASK (~T1_IDLE_STOP)
56 
57 #define T1_GATE_ON 0x0040 /* Timer Gate time accumulation enabled */
58 #define T1_GATE_OFF 0x0000 /* Timer Gate time accumulation disabled */
59 #define T1_GATE_MASK (~T1_GATE_ON)
60 
61 #define T1_PS_1_1 0x0000 /* Prescaler 1:1 */
62 #define T1_PS_1_8 0x0010 /* 1:8 */
63 #define T1_PS_1_64 0x0020 /* 1:64 */
64 #define T1_PS_1_256 0x0030 /* 1:256 */
65 #define T1_PS_MASK (~T1_PS_1_256)
66 
67 #define T1_SYNC_EXT_ON 0x0004 /* Synch external clk input */
68 #define T1_SYNC_EXT_OFF 0x0000 /* Do not synch external clk input */
69 #define T1_SYNC_EXT_MASK (~T1_SYNC_EXT_ON)
70 
71 #define T1_SOURCE_EXT 0x0002 /* External clock source */
72 #define T1_SOURCE_INT 0x0000 /* Internal clock source */
73 #define T1_SOURCE_MASK (~T1_SOURCE_EXT)
74 
75 #ifdef _T2IF
76 /* T2CON: TIMER2 CONTROL REGISTER */
77 #define T2_ON 0x8000 /* Timer2 ON */
78 #define T2_OFF 0x0000 /* Timer2 OFF */
79 #define T2_OFF_ON_MASK (~T2_ON)
80 
81 #define T2_IDLE_STOP 0x2000 /* stop operation during sleep */
82 #define T2_IDLE_CON 0x0000 /* operate during sleep */
83 #define T2_IDLE_MASK (~T2_IDLE_STOP)
84 
85 #define T2_GATE_ON 0x0040 /* Timer Gate time accumulation enabled */
86 #define T2_GATE_OFF 0x0000 /* Timer Gate time accumulation disabled */
87 #define T2_GATE_MASK (~T2_GATE_ON)
88 
89 #define T2_PS_1_1 0x0000 /* Prescaler 1:1 */
90 #define T2_PS_1_8 0x0010 /* 1:8 */
91 #define T2_PS_1_64 0x0020 /* 1:64 */
92 #define T2_PS_1_256 0x0030 /* 1:256 */
93 #define T2_PS_MASK (~T2_PS_1_256)
94 
95 #define T2_32BIT_MODE_ON 0x0008 /* Timer 2 and Timer 3 form a 32 bit Timer */
96 #define T2_32BIT_MODE_OFF 0x0000
97 #define T2_32BIT_MODE_MASK (~T2_32BIT_MODE_ON)
98 
99 #define T2_SOURCE_EXT 0x0002 /* External clock source */
100 #define T2_SOURCE_INT 0x0000 /* Internal clock source */
101 #define T2_SOURCE_MASK (~T2_SOURCE_EXT)
102 #endif
103 
104 #ifdef _T3IF
105 /* T3CON: TIMER3 CONTROL REGISTER */
106 #define T3_ON 0x8000 /* Timer3 ON */
107 #define T3_OFF 0x0000 /* Timer3 OFF */
108 #define T3_OFF_ON_MASK (~T3_ON)
109 
110 #define T3_IDLE_STOP 0x2000 /* operate during sleep */
111 #define T3_IDLE_CON 0x0000 /* stop operation during sleep */
112 #define T3_IDLE_MASK (~T3_IDLE_STOP)
113 
114 #define T3_GATE_ON 0x0040 /* Timer Gate time accumulation enabled */
115 #define T3_GATE_OFF 0x0000 /* Timer Gate time accumulation disabled */
116 #define T3_GATE_MASK (~T3_GATE_ON)
117 
118 #define T3_PS_1_1 0x0000 /* Prescaler 1:1 */
119 #define T3_PS_1_8 0x0010 /* 1:8 */
120 #define T3_PS_1_64 0x0020 /* 1:64 */
121 #define T3_PS_1_256 0x0030 /* 1:256 */
122 #define T3_PS_MASK (~T3_PS_1_256)
123 
124 #define T3_SOURCE_EXT 0x0002 /* External clock source */
125 #define T3_SOURCE_INT 0x0000 /* Internal clock source */
126 #define T3_SOURCE_MASK (~T3_SOURCE_EXT)
127 #endif
128 
129 #ifdef _T4IF
130 /* T4CON: TIMER4 CONTROL REGISTER */
131 #define T4_ON 0x8000 /* Timer4 ON */
132 #define T4_OFF 0x0000 /* Timer4 OFF */
133 #define T4_OFF_ON_MASK (~T4_ON)
134 
135 #define T4_IDLE_STOP 0x2000 /* operate during sleep */
136 #define T4_IDLE_CON 0x0000 /* stop operation during sleep */
137 #define T4_IDLE_MASK (~T4_IDLE_STOP)
138 
139 #define T4_GATE_ON 0x0040 /* Timer Gate time accumulation enabled */
140 #define T4_GATE_OFF 0x0000 /* Timer Gate time accumulation disabled */
141 #define T4_GATE_MASK (~T4_GATE_ON)
142 
143 #define T4_PS_1_1 0x0000 /* Prescaler 1:1 */
144 #define T4_PS_1_8 0x0010 /* 1:8 */
145 #define T4_PS_1_64 0x0020 /* 1:64 */
146 #define T4_PS_1_256 0x0030 /* 1:256 */
147 #define T4_PS_MASK (~T4_PS_1_256)
148 
149 #define T4_32BIT_MODE_ON 0x0008 /* Timer 4 and Timer 5 form a 32 bit Timer */
150 #define T4_32BIT_MODE_OFF 0x0000
151 #define T4_32BIT_MODE_MASK (~T4_32BIT_MODE_ON)
152 
153 #define T4_SOURCE_EXT 0x0002 /* External clock source */
154 #define T4_SOURCE_INT 0x0000 /* Internal clock source */
155 #define T4_SOURCE_MASK (~T4_SOURCE_EXT)
156 #endif
157 
158 #ifdef _T5IF
159 /* T5CON: TIMER5 CONTROL REGISTER */
160 #define T5_ON 0x8000 /* Timer5 ON */
161 #define T5_OFF 0x0000 /* Timer5 OFF */
162 #define T5_OFF_ON_MASK (~T5_ON)
163 
164 #define T5_IDLE_STOP 0x2000 /* operate during sleep */
165 #define T5_IDLE_CON 0x0000 /* stop operation during sleep */
166 #define T5_IDLE_MASK (~T5_IDLE_STOP)
167 
168 #define T5_GATE_ON 0x0040 /* Timer Gate time accumulation enabled */
169 #define T5_GATE_OFF 0x0000 /* Timer Gate time accumulation disabled */
170 #define T5_GATE_MASK (~T5_GATE_ON)
171 
172 #define T5_PS_1_1 0x0000 /* Prescaler 1:1 */
173 #define T5_PS_1_8 0x0010 /* 1:8 */
174 #define T5_PS_1_64 0x0020 /* 1:64 */
175 #define T5_PS_1_256 0x0030 /* 1:256 */
176 #define T5_PS_MASK (~T5_PS_1_256)
177 
178 #define T5_SOURCE_EXT 0x0002 /* External clock source */
179 #define T5_SOURCE_INT 0x0000 /* Internal clock source */
180 #define T5_SOURCE_MASK (~T5_SOURCE_EXT)
181 #endif
182 
183 #ifdef _T6IF
184 /* T6CON: TIMER6 CONTROL REGISTER */
185 #define T6_ON 0x8000 /* Timer6 ON */
186 #define T6_OFF 0x0000 /* Timer6 OFF */
187 #define T6_OFF_ON_MASK (~T6_ON)
188 
189 #define T6_IDLE_STOP 0x2000 /* operate during sleep */
190 #define T6_IDLE_CON 0x0000 /* stop operation during sleep */
191 #define T6_IDLE_MASK (~T6_IDLE_STOP)
192 
193 #define T6_GATE_ON 0x0040 /* Timer Gate time accumulation enabled */
194 #define T6_GATE_OFF 0x0000 /* Timer Gate time accumulation disabled */
195 #define T6_GATE_MASK (~T6_GATE_ON)
196 
197 #define T6_PS_1_1 0x0000 /* Prescaler 1:1 */
198 #define T6_PS_1_8 0x0010 /* 1:8 */
199 #define T6_PS_1_64 0x0020 /* 1:64 */
200 #define T6_PS_1_256 0x0030 /* 1:256 */
201 #define T6_PS_MASK (~T6_PS_1_256)
202 
203 #define T6_32BIT_MODE_ON 0x0008 /* Timer 6 and Timer 7 form a 32 bit Timer */
204 #define T6_32BIT_MODE_OFF 0x0000
205 #define T6_32BIT_MODE_MASK (~T6_32BIT_MODE_ON)
206 
207 #define T6_SOURCE_EXT 0x0002 /* External clock source */
208 #define T6_SOURCE_INT 0x0000 /* Internal clock source */
209 #define T6_SOURCE_MASK (~T6_SOURCE_EXT)
210 #endif
211 
212 #ifdef _T7IF
213 /* T7CON: TIMER7 CONTROL REGISTER */
214 #define T7_ON 0x8000 /* Timer7 ON */
215 #define T7_OFF 0x0000 /* Timer7 OFF */
216 #define T7_OFF_ON_MASK (~T7_ON)
217 
218 #define T7_IDLE_STOP 0x2000 /* operate during sleep */
219 #define T7_IDLE_CON 0x0000 /* stop operation during sleep */
220 #define T7_IDLE_MASK (~T7_IDLE_STOP)
221 
222 #define T7_GATE_ON 0x0040 /* Timer Gate time accumulation enabled */
223 #define T7_GATE_OFF 0x0000 /* Timer Gate time accumulation disabled */
224 #define T7_GATE_MASK (~T7_GATE_ON)
225 
226 #define T7_PS_1_1 0x0000 /* Prescaler 1:1 */
227 #define T7_PS_1_8 0x0010 /* 1:8 */
228 #define T7_PS_1_64 0x0020 /* 1:64 */
229 #define T7_PS_1_256 0x0030 /* 1:256 */
230 #define T7_PS_MASK (~T7_PS_1_256)
231 
232 #define T7_SOURCE_EXT 0x0002 /* External clock source */
233 #define T7_SOURCE_INT 0x0000 /* Internal clock source */
234 #define T7_SOURCE_MASK (~T7_SOURCE_EXT)
235 #endif
236 
237 #ifdef _T8IF
238 /* T8CON: TIMER8 CONTROL REGISTER */
239 #define T8_ON 0x8000 /* Timer8 ON */
240 #define T8_OFF 0x0000 /* Timer8 OFF */
241 #define T8_OFF_ON_MASK (~T8_ON)
242 
243 #define T8_IDLE_STOP 0x2000 /* operate during sleep */
244 #define T8_IDLE_CON 0x0000 /* stop operation during sleep */
245 #define T8_IDLE_MASK (~T8_IDLE_STOP)
246 
247 #define T8_GATE_ON 0x0040 /* Timer Gate time accumulation enabled */
248 #define T8_GATE_OFF 0x0000 /* Timer Gate time accumulation disabled */
249 #define T8_GATE_MASK (~T8_GATE_ON)
250 
251 #define T8_PS_1_1 0x0000 /* Prescaler 1:1 */
252 #define T8_PS_1_8 0x0010 /* 1:8 */
253 #define T8_PS_1_64 0x0020 /* 1:64 */
254 #define T8_PS_1_256 0x0030 /* 1:256 */
255 #define T8_PS_MASK (~T8_PS_1_256)
256 
257 #define T8_32BIT_MODE_ON 0x0008 /* Timer 8 and Timer 9 form a 32 bit Timer */
258 #define T8_32BIT_MODE_OFF 0x0000
259 #define T8_32BIT_MODE_MASK (~T8_32BIT_MODE_ON)
260 
261 #define T8_SOURCE_EXT 0x0002 /* External clock source */
262 #define T8_SOURCE_INT 0x0000 /* Internal clock source */
263 #define T8_SOURCE_MASK (~T8_SOURCE_EXT)
264 #endif
265 
266 #ifdef _T9IF
267 /* T9CON: TIMER9 CONTROL REGISTER */
268 #define T9_ON 0x8000 /* Timer9 ON */
269 #define T9_OFF 0x0000 /* Timer9 OFF */
270 #define T9_OFF_ON_MASK (~T9_ON)
271 
272 #define T9_IDLE_STOP 0x2000 /* operate during sleep */
273 #define T9_IDLE_CON 0x0000 /* stop operation during sleep */
274 #define T9_IDLE_MASK (~T9_IDLE_STOP)
275 
276 #define T9_GATE_ON 0x0040 /* Timer Gate time accumulation enabled */
277 #define T9_GATE_OFF 0x0000 /* Timer Gate time accumulation disabled */
278 #define T9_GATE_MASK (~T9_GATE_ON)
279 
280 #define T9_PS_1_1 0x0000 /* Prescaler 1:1 */
281 #define T9_PS_1_8 0x0010 /* 1:8 */
282 #define T9_PS_1_64 0x0020 /* 1:64 */
283 #define T9_PS_1_256 0x0030 /* 1:256 */
284 #define T9_PS_MASK (~T9_PS_1_256)
285 
286 #define T9_SOURCE_EXT 0x0002 /* External clock source */
287 #define T9_SOURCE_INT 0x0000 /* Internal clock source */
288 #define T9_SOURCE_MASK (~T9_SOURCE_EXT)
289 #endif
290 
291 //Input Capture macros
292 
293 /*
294 The following macros are a subset of the AND/OR macros found in the
295 the MPLAB C30/src/peripheral_24F/incap.h file and placed
296 in this header for use solely and exclusively on Microchip
297 PICmicro Microcontroller products as
298 specified in the MPLAB C30/src/peripheral_24F/incap.h header.
299 */
300 #if (defined(__dsPIC33E__) || defined(__PIC24E__))
301 #define IC_IDLE_STOP 0x2000 /* IC stop in sleep mode */
302 #define IC_IDLE_CON 0x0000 /* IC operate in sleep mode */
303 #define IC_IDLE_MASK (~IC_IDLE_STOP)
304 
305 #define IC_TIMER2_SRC (1 << 10) /* Timer2 is the clock source for Capture */
306 #define IC_TIMER3_SRC 0x0000 /* Timer3 is the clock source for Capture */
307 #define IC_TIMER_SRC_MASK (~ (7 << 10) )
308 
309 #define IC_INT_4CAPTURE 0x0060 /* Interrupt on fourth Capture*/
310 #define IC_INT_3CAPTURE 0x0040 /* Interrupt on third Capture */
311 #define IC_INT_2CAPTURE 0x0020 /* Interrupt on second Capture*/
312 #define IC_INT_1CAPTURE 0x0000 /* Interrupt on first Capture */
313 #define IC_INT_CAPTURE_MASK (~IC_INT_4CAPTURE)
314 
315 #define IC_INTERRUPT 0x0007 /* Interrupt pin only in CPU sleep and idle mode */
316 #define IC_EVERY_16_RISE_EDGE 0x0005 /* Every 16th rising edge */
317 #define IC_EVERY_4_RISE_EDGE 0x0004 /* Every 4th rising edge */
318 #define IC_EVERY_RISE_EDGE 0x0003 /* Every rising edge */
319 #define IC_EVERY_FALL_EDGE 0x0002 /* Every falling edge */
320 #define IC_EVERY_EDGE 0x0001 /* Every rising/falling edge */
321 #define IC_INPUTCAP_OFF 0x0000 /* Input Capture Off */
322 #define IC_CAPTURE_MODE_MASK (~IC_INTERRUPT)
323 
324 #else
325 #define IC_IDLE_STOP 0x2000 /* IC stop in sleep mode */
326 #define IC_IDLE_CON 0x0000 /* IC operate in sleep mode */
327 #define IC_IDLE_MASK (~IC_IDLE_STOP)
328 
329 #define IC_TIMER2_SRC 0x0080 /* Timer2 is the clock source for Capture */
330 #define IC_TIMER3_SRC 0x0000 /* Timer3 is the clock source for Capture */
331 #define IC_TIMER_SRC_MASK (~IC_TIMER2_SRC)
332 
333 #define IC_INT_4CAPTURE 0x0060 /* Interrupt on fourth Capture*/
334 #define IC_INT_3CAPTURE 0x0040 /* Interrupt on third Capture */
335 #define IC_INT_2CAPTURE 0x0020 /* Interrupt on second Capture*/
336 #define IC_INT_1CAPTURE 0x0000 /* Interrupt on first Capture */
337 #define IC_INT_CAPTURE_MASK (~IC_INT_4CAPTURE)
338 
339 #define IC_INTERRUPT 0x0007 /* Interrupt pin only in CPU sleep and idle mode */
340 #define IC_EVERY_16_RISE_EDGE 0x0005 /* Every 16th rising edge */
341 #define IC_EVERY_4_RISE_EDGE 0x0004 /* Every 4th rising edge */
342 #define IC_EVERY_RISE_EDGE 0x0003 /* Every rising edge */
343 #define IC_EVERY_FALL_EDGE 0x0002 /* Every falling edge */
344 #define IC_EVERY_EDGE 0x0001 /* Every rising/falling edge */
345 #define IC_INPUTCAP_OFF 0x0000 /* Input Capture Off */
346 #define IC_CAPTURE_MODE_MASK (~IC_INTERRUPT)
347 #endif
348 
349 //Output Compare macros
350 
351 /*
352 The following macros are a subset of the AND/OR macros found in the
353 the MPLAB C30/src/peripheral_24F/outcompare.h file and placed
354 in this header for use solely and exclusively on Microchip
355 PICmicro Microcontroller products as
356 specified in the MPLAB C30/src/peripheral_24F/outcompare.h header.
357 */
358 
359 #if (defined(__dsPIC33E__) || defined(__PIC24E__))
360 #define OC_IDLE_CON 0x0000 /* continue operation in idle mode */
361 #define OC_IDLE_STOP 0x2000 /* stop in idle mode */
362 #define OC_IDLE_MASK (~OC_IDLE_STOP)
363 #define OC_TIMER2_SRC 0x0000 /* Timer2 is the clock source for OutputCompare */
364 #define OC_TIMER3_SRC (1 << 10) /* Timer3 is the clock source for OutputCompare */
365 #define OC_TIMER_SRC_MASK (~ (7 << 10) )
366 
367 #define OC_PWM_CENTER_ALIGN 0x0007 /* PWM Mode on OCx, fault pin enabled, (TxIF bit is set for PWM, OCxIF is set for fault)*/
368 #define OC_PWM_EDGE_ALIGN 0x0006 /* PWM Mode on OCx, fault pin disabled */
369 #define OC_CONTINUE_PULSE 0x0005 /* Generates Continuous Output pulse on OCx Pin */
370 #define OC_SINGLE_PULSE 0x0004 /* Generates Single Output pulse on OCx Pin */
371 #define OC_TOGGLE_PULSE 0x0003 /* Compare1 toggles OCx pin*/
372 #define OC_HIGH_LOW 0x0002 /* Compare1 forces OCx pin Low*/
373 #define OC_LOW_HIGH 0x0001 /* Compare1 forces OCx pin High*/
374 #define OC_OFF 0x0000 /* OutputCompare x Off*/
375 #define OC_PWM_MODE_MASK (~OC_PWM_FAULT_PIN_ENABLE)
376 
377 #define OC_PWM_FAULT_PIN_ENABLE 0x0007 /* PWM Mode on OCx, keep for compatibility with PIC24H source*/
378 #define OC_PWM_FAULT_PIN_DISABLE 0x0006 /* PWM Mode on OCx, keep for compatibility with PIC24H source */
379 
380 #else
381 /* Section : Output Compare Stop in Idle mode Bit defines */
382 #define OC_IDLE_CON 0x0000 /* continue operation in idle mode */
383 #define OC_IDLE_STOP 0x2000 /* stop in idle mode */
384 #define OC_IDLE_MASK (~OC_IDLE_STOP)
385 
386 /*Section : Output Compare timer select Bit Defines */
387 #define OC_TIMER2_SRC 0x0000 /* Timer2 is the clock source for OutputCompare */
388 #define OC_TIMER3_SRC 0x0008 /* Timer3 is the clock source for OutputCompare */
389 #define OC_TIMER_SRC_MASK (~OC_TIMER3_SRC)
390 
391 #define OC_PWM_FAULT_PIN_ENABLE 0x0007 /* PWM Mode on OCx, fault pin enabled, (TxIF bit is set for PWM, OCxIF is set for fault)*/
392 #define OC_PWM_FAULT_PIN_DISABLE 0x0006 /* PWM Mode on OCx, fault pin disabled */
393 #define OC_CONTINUE_PULSE 0x0005 /* Generates Continuous Output pulse on OCx Pin */
394 #define OC_SINGLE_PULSE 0x0004 /* Generates Single Output pulse on OCx Pin */
395 #define OC_TOGGLE_PULSE 0x0003 /* Compare1 toggles OCx pin*/
396 #define OC_HIGH_LOW 0x0002 /* Compare1 forces OCx pin Low*/
397 #define OC_LOW_HIGH 0x0001 /* Compare1 forces OCx pin High*/
398 #define OC_OFF 0x0000 /* OutputCompare x Off*/
399 #define OC_PWM_MODE_MASK (~OC_PWM_FAULT_PIN_ENABLE)
400 #endif
401 
402 
403 #endif
404