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pic24_spi.h
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1 /* Standard copyright does not go in this file because
2 * of the use of Microchip provided macros, see comments below.
3 */
4 
5 
6 // Documentation for this file. If the \file tag isn't present,
7 // this file won't be documented.
8 /** \file
9  * SPI module support functions.
10  */
11 
12 #include <stdint.h>
13 #include "pic24_chip.h"
14 
15 
16 #ifndef _PIC24_SPI_H_
17 #define _PIC24_SPI_H_
18 /*
19 The following macros are a subset of the AND/OR macros found in the
20 the MPLAB C30/src/peripheral_24F/spi.h file and placed
21 in this header for use solely and exclusively on Microchip
22 PICmicro Microcontroller products as
23 specified in the MPLAB C30/src/peripheral_24F/spi.h header.
24 */
25 
26 /* SPIXCON1: SPIx CONTROL REGISTER 1 */
27 #define DISABLE_SCK_PIN 0x1000 /* SCK pin is not used by module */
28 #define ENABLE_SCK_PIN 0x0000 /* SCK pin is used by module */
29 #define SCK_PIN_MASK (~DISABLE_SCK_PIN)
30 
31 #define DISABLE_SDO_PIN 0x0800 /* SDO pin is not used by module */
32 #define ENABLE_SDO_PIN 0x0000 /* SDO pin is used by module */
33 #define SDO_PIN_MASK (~DISABLE_SDO_PIN)
34 
35 #define SPI_MODE16_ON 0x0400 /* Communication is word wide */
36 #define SPI_MODE8_ON 0x0000 /* Communication is byte wide */
37 #define SPI_MODE_MASK (~SPI_MODE16_ON)
38 
39 #define SPI_SMP_ON 0x0200 /* Input data sampled at end of data output time */
40 #define SPI_SMP_OFF 0x0000 /* Input data sampled at middle of data output time */
41 #define SPI_SMP_MASK (~SPI_SMP_ON)
42 
43 #define SPI_CKE_ON 0x0100 /* Transmit happens from active clock state to idle clock state*/
44 #define SPI_CKE_OFF 0x0000 /* Transmit happens on transition from idle clock state to active clock state */
45 #define SPI_CKE_MASK (~SPI_CKE_ON)
46 
47 #define SLAVE_ENABLE_ON 0x0080 /* Slave Select enbale */
48 #define SLAVE_ENABLE_OFF 0x0000 /* Slave Select not used by module */
49 #define SLAVE_ENABLE_MASK (~SLAVE_ENABLE_ON)
50 
51 #define CLK_POL_ACTIVE_LOW 0x0040 /* Idle state for clock is high, active is low */
52 #define CLK_POL_ACTIVE_HIGH 0x0000 /* Idle state for clock is low, active is high */
53 #define CLK_POL_ACTIVE_MASK (~CLK_POL_ACTIVE_LOW)
54 
55 #define MASTER_ENABLE_ON 0x0020 /* Master Mode */
56 #define MASTER_ENABLE_OFF 0x0000 /* Slave Mode */
57 #define MASTER_ENABLE_MASK (~MASTER_ENABLE_ON)
58 
59 #define SEC_PRESCAL_1_1 0x001c /* Secondary Prescale 1:1 */
60 #define SEC_PRESCAL_2_1 0x0018 /* Secondary Prescale 2:1 */
61 #define SEC_PRESCAL_3_1 0x0014 /* Secondary Prescale 3:1 */
62 #define SEC_PRESCAL_4_1 0x0010/* Secondary Prescale 4:1 */
63 #define SEC_PRESCAL_5_1 0x000c /* Secondary Prescale 5:1 */
64 #define SEC_PRESCAL_6_1 0x0008/* Secondary Prescale 6:1 */
65 #define SEC_PRESCAL_7_1 0x0004 /* Secondary Prescale 7:1 */
66 #define SEC_PRESCAL_8_1 0x0000 /* Secondary Prescale 8:1 */
67 #define SEC_PRESCAL_MASK (~SEC_PRESCAL_1_1)
68 
69 #define PRI_PRESCAL_1_1 0x0003 /* Primary Prescale 1:1 */
70 #define PRI_PRESCAL_4_1 0x0002 /* Primary Prescale 4:1 */
71 #define PRI_PRESCAL_16_1 0x0001 /* Primary Prescale 16:1 */
72 #define PRI_PRESCAL_64_1 0x0000 /* Primary Prescale 64:1 */
73 #define PRI_PRESCAL_MASK (~PRI_PRESCAL_1_1)
74 
75 /* SPIxSTAT REGISTER */
76 #define SPI_ENABLE 0x8000 /* Enable module */
77 #define SPI_DISABLE 0x0000 /* Disable module */
78 #define SPI_ENBL_DSBL_MASK (~SPI_ENABLE)
79 
80 #define SPI_IDLE_STOP 0x2000 /* Discontinue module operation in idle mode */
81 #define SPI_IDLE_CON 0x0000 /* Continue module operation in idle mode */
82 #define SPI_IDLE_MASK (~SPI_IDLE_STOP)
83 
84 #define SPI_RX_OVFLOW 0x0040
85 #define SPI_RX_OVFLOW_CLR 0x0000 /* Clear receive overflow bit */
86 
87 /* SPIxCON2: SPIx CONTROL REGISTER 2 */
88 #define FRAME_ENABLE_ON 0x8000 /* Frame SPI support enable */
89 #define FRAME_ENABLE_OFF 0x0000 /* Frame SPI support Disable */
90 #define FRAME_ENABLE_MASK (~FRAME_ENABLE_ON)
91 
92 #define FRAME_SYNC_INPUT 0x4000 /* Frame sync pulse Input (slave) */
93 #define FRAME_SYNC_OUTPUT 0x0000 /* Frame sync pulse Output (master)*/
94 #define FRAME_SYNC_MASK (~FRAME_SYNC_INPUT)
95 
96 #define FRAME_SYNC_ACTIVE_HIGH 0x2000 /* Frame sync pulse Input (slave) */
97 #define FRAME_SYNC_ACTIVE_LOW 0x0000 /* Frame sync pulse Output (master)*/
98 #define FRAME_SYNC_POL_MASK (~FRAME_SYNC_ACTIVE_HIGH)
99 
100 #define SPI_FRM_PULSE_FIRST_CLK 0x0002 /* frame pulse coincides with the first bit clock */
101 #define SPI_FRM_PULSE_PREV_CLK 0x0000 /* frame pulse precedes the first bit clock */
102 #define SPI_FRM_PULSE_MASK (~SPI_FRM_PULSE_FIRST_CLK)
103 
104 #define SPI_ENH_BUFF_ENABLE 0x0001 /* enable enhanced buffer */
105 #define SPI_ENH_BUFF_DISABLE 0x0000 /* disable enhanced buffer */
106 #define SPI_ENH_BUFF_MASK (~SPI_ENH_BUFF_ENABLE)
107 
108 // Only include if this UART exists.
109 #if (NUM_SPI_MODS >= 1)
111 #endif
112 
113 
114 #if (NUM_SPI_MODS >= 2)
115 uint16_t ioMasterSPI2(uint16_t u16_c);
116 #endif
117 
118 
119 #endif